IDTP9122

Advanced Datasheet

March 12, 2014

8

© 2014 Integrated Device Technology, Inc.

Mode0

– Individual Buck control

With IDTP9122 configured for mode0, both regulators are individually controlled via ENx input pin. The PORB output can be

configured to indicate various power up conditions.

Mode1

– Do not use - reserved

Mode2

– Master Enable pin (MEN) with sequence

With IDTP9122 configured for mode2, a configurable state machine will ramp up/down both regulators controlled by the MEN

pin. The PORB output can be configured to indicate various power up conditions. Individual Power Good output pins indicate

the regulator output being established.

Mode3

– Master Enable pin (MEN) with sequence and Standby Mode

With IDTP9122 configured for mode3, a configurable state machine will ramp up/down both regulators controlled by the MEN

pin. The PORB output can be configured to indicate various power up conditions. Individual Power Good output pins indicate

the regulator output being established.

In addition to mode2, mode3 supports the STANDBY mode entered by asserting the STANDBY pin. During standby, Buck1

and/or

2

will

be

turned

off

without

sequencing.

The

configuration

is

configurable

via

OTP.

Pin Description

DEVSLPIN

This pin allows the IC to enter and exit SLEEP mode. Sleep mode is the lowest power state of the device and is activated when

DEVSLPIN is logic HIGH. The device will be on “normal operation” when DEVSLPIN is logic LOW. See figure 2 – Device Power States.

VINSEL

This pin allows the function of Buck 2 to be changed to a Switch function. Logic LOW on this pin puts the channel into Buck configuration,

and a Logic HIGH on this pin puts the channel into Switch configuration.

PVIN1, PVIN2

PVINx is each buck converters’ respective power supply input. They provide power to the internal MOSFETs for the switch mode regulator.

Their operating range is 2.7V to 5.5V, and a 10uF capacitor is be placed as close as possible to each of the respective pins. An second

10uF capacitor should be used with PVIN2 because of the greater current sourcing capability of this channel. Because capacitance

derates with voltage, a 10V rated X7R ceramic capacitors be used. X7R is preferred over X5R because the derating with X7R is less. For

best performance, each of these power supply inputs are to be connected together on a dedicated circuit board power plane, and that the

trace going from these pins to the dedicated power plane be made as short as possible. Y5V capacitors are not recommended because of

their general low performance with respect to temperature, voltage derating, and higher resistance at high frequency’s minimizing their

ability to filter out high frequency noise.

VIN

VIN is the power supply input for the rest of the integrated circuit. It too has an operating range of 2.7V to 5.5V, and a 2.2uF 10V rated

X7R capacitor should be placed as close as possible to its’ pin. VIN should also be tied to the same power plane that the PVINx pins are

tied to with as short a trace as possible. Y5V capacitors are highly not recommended.

PGND1, PGND2

These are the dedicated ground pins for each of the respective power supply’s. The traces from these pins, to a dedicated ground plane,

should be made as short as possible.

VGND