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REJ03F0035_M61524FP Datasheet(PDF) 6 Page - Hitachi Semiconductor |
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REJ03F0035_M61524FP Datasheet(HTML) 6 Page - Hitachi Semiconductor |
6 / 21 page M61524FP Rev.1.0, Sep.19.2003, page 6 of 20 Recommended Operating Condition (Ta=25°C, unless otherwise noted) Limits Parameter Symbol Conditions MIN TYP MAX Units Supply voltage VCC 8 9 10 V Logic “H” level input voltage VIH VCC=9V GND reference 2.2 — 5.5 V Logic “L” level input voltage VIL VCC=9V GND reference 0 — 0.6 V Relationship between Data and Clock D0 D1 D2 D3 D13 D14 D15 CLOCK DATA Data signal is read atthe rising edgeof CLOCK. Make "H" at the timing which DATA of D0-D15 make latch. When DATA is "H", latch signal is created at the falling edge of CLOCK. |
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