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S6BP401AE1SN1B000 Datasheet(PDF) 8 Page - Cypress Semiconductor |
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S6BP401AE1SN1B000 Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 38 page  Document Number: 002-03341 Rev.*C Page 8 of 38 S6BP401A 5. Architecture Block Diagram Figure 5-1 Architechture Block Diagram Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en1 Voltage Reference Power Good Monitor Peak Current Comparator FB1 PVCC1 LX1 PGND1 << DD1 >> PGND2 PVCC2 LX2 Discharge ss1 clk pg1 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en2 Voltage Reference Power Good Monitor Peak Current Comparator FB2 PVCC2 LX2 PGND2 << DD2 >> Discharge ss2 clk pg2 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en3 Voltage Reference Power Good Monitor Peak Current Comparator FB3 PVCC3 LX3 PGND3 << DD3 >> Discharge ss3 clk pg3 Error Amplifier Slope Compensation PWM Logic Control PWM Comparator Current Sense Anti- Shoot Through Low Priority en4 Voltage Reference Power Good Monitor Peak Current Comparator FB4 PVCC4 LX4 PGND4 << DD4 >> Discharge ss4 clk pg4 |
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