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MB96F653ABPMC-GSE2 Datasheet(PDF) 2 Page - Cypress Semiconductor |
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MB96F653ABPMC-GSE2 Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 65 page Document Number: 002-04707 Rev.*A Page 2 of 65 MB96650 Series Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device Extended support for LIN-Protocol to reduce interrupt load I 2C Up to 400kbps Master and Slave functionality, 7-bit and 10-bit addressing A/D converter SAR-type 8/10-bit resolution Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger, reload timers and PPGs Range Comparator Function Scan Disable Function Source Clock Timers Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer) Hardware Watchdog Timer Hardware watchdog timer is active after reset Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval Reload Timers 16-bit wide Prescaler with 1/21, 1/22, 1/23, 1/24, 1/25, 1/26 of peripheral clock frequency Event count function Free-Running Timers Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4) Prescaler with 1, 1/21, 1/22, 1/23, 1/24, 1/25, 1/26, 1/27, 1/28 of peripheral clock frequency Input Capture Units 16-bit wide Signals an interrupt upon external event Rising edge, Falling edge or Both (rising & falling) edges sensitive Output Compare Units 16-bit wide Signals an interrupt when a match with Free-running Timer occurs A pair of compare registers can be used to generate an output signal Programmable Pulse Generator 16-bit down counter, cycle and duty setting registers Can be used as 2 8-bit PPG Interrupt at trigger, counter borrow and/or duty match PWM operation and one-shot operation Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected Reload timer underflow as clock input Can be triggered by software or reload timer Can trigger ADC conversion Timing point capture Start delay Quadrature Position/Revolution Counter (QPRC) Up/down count mode, Phase difference count mode, Count mode with direction 16-bit position counter 16-bit revolution counter Two 16-bit compare registers with interrupt Detection edge of the three external event input pins AIN, BIN and ZIN is configurable Real Time Clock Operational on main oscillation (4MHz), sub oscillation (32kHz) or RC oscillation (100kHz/2MHz) Capable to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration) Read/write accessible second/minute/hour registers Can signal interrupts every half second/second/minute/hour/day Internal clock divider and prescaler provide exact 1s clock External Interrupts Edge or Level sensitive Interrupt mask bit per channel Each available CAN channel RX has an external interrupt for wake-up Selected USART channels SIN have an external interrupt for wake-up Non Maskable Interrupt Disabled after reset, can be enabled by Boot-ROM depending on ROM configuration block |
Similar Part No. - MB96F653ABPMC-GSE2 |
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Similar Description - MB96F653ABPMC-GSE2 |
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