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AD5676ACPZ-REEL7 Datasheet(PDF) 11 Page - Analog Devices |
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AD5676ACPZ-REEL7 Datasheet(HTML) 11 Page - Analog Devices |
11 / 28 page AD5676 Data Sheet Rev. B | Page 10 of 27 14 13 12 1 3 4 RESET 15 VREF SDO LDAC 11 GND VDD SYNC 2 VLOGIC SCLK 5 SDI NIC = NOT INTERNALLY CONNECTED AD5676 TOP VIEW (Not to Scale) Figure 6. 20-Lead LFCSP Pin Configuration Table 8. 20-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. The AD5676 operate from 2.7 V to 5.5 V. Decouple VDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 2 VLOGIC Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V. 3 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data transfers in on the falling edges of the next 24 clocks. 4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data transfers at rates of up to 50 MHz. 5 SDI Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 6 VOUT7 Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation. 7 VOUT6 Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation. 8 VOUT5 Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation. 9 VOUT4 Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation. 10, 16 NIC Not Internally Connected 11 GND Ground Reference Point for All Circuitry on the Device. 12 LDAC Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. That allows all DAC outputs to simultaneously update. This pin can also be tied permanently low. 13 SDO Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge. 14 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. 15 VREF Reference Input Voltage. 17 VOUT3 Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation. 18 VOUT2 Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation. 19 VOUT1 Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation. 20 VOUT0 Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation. EPAD Exposed Pad. The exposed pad must be tied to GND. |
Similar Part No. - AD5676ACPZ-REEL7 |
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Similar Description - AD5676ACPZ-REEL7 |
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