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AD7172-2 Datasheet(PDF) 6 Page - Analog Devices |
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AD7172-2 Datasheet(HTML) 6 Page - Analog Devices |
6 / 61 page Data Sheet AD7172-2 Rev. A | Page 5 of 60 Parameter Test Conditions/Comments Min Typ Max Unit EXTERNAL REFERENCE INPUTS Differential Input Range VREF = (REF+) − (REF−) 1 2.5 AVDD1 V Absolute Voltage Limits1 Input Buffers Disabled AVSS − 0.05 AVDD1 + 0.05 V Input Buffers Enabled AVSS AVDD1 V REFIN Input Current Input Buffers Disabled Input Current ±9 µA/V Input Current Drift External clock ±100 pA/V/°C Internal clock ±0.75 nA/V/°C Input Buffers Enabled Input Current ±100 nA Input Current Drift ±0.25 nA/°C Normal Mode Rejection1 See the Rejection parameter Common-Mode Rejection 95 dB TEMPERATURE SENSOR Accuracy After user calibration at 25°C ±2 °C Sensitivity 477 µV/K BURNOUT CURRENTS Source/Sink Current Analog input buffers must be enabled ±10 µA GPIO (GPIO0, GPIO1) With respect to AVSS Input Mode Leakage Current1 −10 +10 µA Floating State Output Capacitance 5 pF Output High Voltage, VOH1 ISOURCE = 200 µA AVSS + 4 V Output Low Voltage, VOL1 ISINK = 800 µA AVSS + 0.4 V Input High Voltage, VIH1 AVSS + 3 V Input Low Voltage, VIL1 AVSS + 0.7 V CLOCK Internal Clock Frequency 2 MHz Accuracy −2.5% +2.5% % Duty Cycle 50 % Output Low Voltage, VOL 0.4 V Output High Voltage, VOH 0.8 × IOVDD V Crystal Frequency 14 16 16.384 MHz Startup Time 10 µs External Clock (CLKIO) 2 2.048 MHz Duty Cycle1 30 50 70 % LOGIC INPUTS Input High Voltage, VINH1 2 V ≤ IOVDD < 2.3 V 0.65 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V Input Low Voltage, VINL1 2 V ≤ IOVDD < 2.3 V 0.35 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V Hysteresis1 IOVDD ≥ 2.7 V 0.08 0.25 V IOVDD < 2.7 V 0.04 0.2 V Leakage Currents −10 +10 µA |
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