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ACT4524 Datasheet(PDF) 8 Page - Active-Semi, Inc

Part # ACT4524
Description  40V/3.5A Buck Converter with Dual Output and Separated Over Current Protection
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Manufacturer  ACTIVE-SEMI [Active-Semi, Inc]
Direct Link  http://www.active-semi.com
Logo ACTIVE-SEMI - Active-Semi, Inc

ACT4524 Datasheet(HTML) 8 Page - Active-Semi, Inc

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ACT4524
Rev 1.1, 22-Feb-16
Innovative PowerTM
- 8 -
www.active-semi.com
Copyright © 2015 Active-Semi, Inc.
APPLICATIONS INFORMATION
Current Sense Resistor
The traces leading to and from the sense resistor
can be significant error sources. With small value
sense resistors, trace resistance shared with the
load
can
cause
significant
errors.
It
is
recommended to connect the sense resistor pads
directly to the CSP and CSN pins using “Kelvin” or
“4-wire” connection techniques as shown below.
PCB Layout Guidance
When laying out the printed circuit board, the
following checklist should be used to ensure proper
operation of the IC.
1) Arrange the power components to reduce the
AC loop size consisting of CIN, VIN pin, SW pin
and the Schottky diode.
2) The high power loss components, e.g. the
controller, Schottky diode, and the inductor
should be placed carefully to make the thermal
spread evenly on the board.
3) Place input decoupling ceramic capacitor CIN as
close to VIN pin as possible. CIN should be
connected to power GND with several vias or
short and wide copper trace.
4) Shottky anode pad and IC exposed pad should
be placed close to ground clips in CLA
applications.
5) Use “Kelvin” or “4-wire” connection techniques
from the sense resistor pads directly to the CSP
and CSN1, CSN2 pins. The CSP ,CSN1, and
CSN2 traces should be in parallel to avoid
interference.
6) Place multiple vias between top and bottom
GND planes for best heat dissipation and noise
immunity.
7) Use short traces connecting HSB-CHSB-SW
loop.
8) SW pad is noise node switching from VIN to
GND. It should be isolated away from the rest
of circuit for good EMI and low noise operation.
PCB Load
Trace
Kevin Sense
Traces
Sense
Resistor
Example PCB Layout
Top Layer
Bottom Layer


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