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ELJ-FAR33MF2 Datasheet(PDF) 5 Page - TriQuint Semiconductor |
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ELJ-FAR33MF2 Datasheet(HTML) 5 Page - TriQuint Semiconductor |
5 / 13 page TriQuint Semiconductor Texas : (972)994 8465 Fax (972)994 8504 Web: www.triquint.com Advance Product Datasheet 5 Notes: 1/ Verified at package level RF test. 2/ Package RF Test Bias: Vd=5 V, adjust Vg1 to achieve Id=65 mA then adjust Vg2 to achieve Id=200mA, Vctrl=+0.2 V 3/ Verified by design, SMT assembled onto a demonstration board detailed on sheet 6. 4/ Vin=250mV, Data Rate = 10.7Gb/s, VD1=VD2T or greater, VCTRL2 and VG2 are adjusted for maximum output. 5/ Computed using RSS Method where Jrms_additive = SQRT(Jrms_out2 - Jrms_in2) 6/ Verified at die level on-wafer probe. 7/ Power Bias Die Probe: Vtee=8 V, adjust Vg to achieve Id=175 mA+/-5%, Vctrl=1.5 V Note: At the die level, drain bias is applied thru the RF output port using a bias tee, voltage is at the DC input to the bias tee. TGA4953EPU Note: Devices designated as EPU are typically early in their characterization process prior to finalizing all electrical and process specifications. Specifications are subject to change without notice. RF SPECIFICATION (Continued) |
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