ZSC31050 Datasheet

© 2017 Integrated Device Technology, Inc.

6

February 13, 2017

No.

Parameter

Symbol

Conditions

Min

Typical

Max

Unit

1.2.5

Analog supply voltage

VDDA

Ratiometric mode

2.7

5.5

V DC

1.2.6

Analog supply voltage

advanced performance

Ratiometric mode

4.5

5.5

V DC

1.2.7

Digital supply voltage

VDD

Externally powered

1.05

VDDA

2.7

V DC

1.2.8

External supply voltage

Voltage Regulator Mode

with external JFET [a]

VDDA +

2V

V DC

1.2.9

Common mode input range[b]

Depends on gain adjust;

refer to section 2.3.1

0.21

0.76

1.2.10

Input voltage FBP pin

-1

VDDA

V DC

1.2.11

Sensor bridge resistance [c]

(over full temperature range)

3.0

25.0

k



Current loop interface,

4 to 20mA

5.0

25.0

k



1.2.12

Reference resistor for bridge

current source *

Bridge current

0.07

1.2.13

Stabilization capacitor *

External capacitor between

VDDA and VSS

50

100

470

nF

1.2.14

VDD stabilization capacitor*, [d]

Between VDD and VSS,

external

0

100

470

nF

1.2.15

Maximum load capacitance

allowed at OUT [e]

Output Voltage Mode

50

nF

1.2.16

Minimum load resistance

allowed

Output Voltage Mode

2

k



1.2.17

Maximum load capacitance

allowed at VGATE

Total capacitance relative to

all potentials

10

nF

[a] Maximum depends on the breakdown voltage of the external JFET; refer to the application recommendations in the ZSC31050 Application

Note—0-10V Output.

[c] No minimum limitation with an external connection between VDDA and VBR.

[d] Lower stabilization capacitors can increase noise level at the output.

[e] If the maximum is used, take into consideration the special requirements of the ZACwire™ interface stated in the ZSC31050 Functional

Description, section 4.3.