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WM8776 Datasheet(PDF) 10 Page - Wolfson Microelectronics plc |
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WM8776 Datasheet(HTML) 10 Page - Wolfson Microelectronics plc |
10 / 55 page WM8776 Product Preview w PP Rev 1.91 June 2004 10 DIGITAL AUDIO INTERFACE – SLAVE MODE ADCBCLK DOUT ADCLRC DIN DACLRC WM8776 CODEC DVD Controller DACBCLK Figure 4 Audio Interface – Slave Mode ADCBCLK/ DACBCLK DACLRC/ ADCLRC t BCH t BCL t BCY DIN DOUT t LRSU t DS t LRH t DH t DD Figure 5 Digital Audio Data Timing – Slave Mode Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information ADC/DACBCLK cycle time tBCY 50 ns ADC/DACBCLK pulse width high tBCH 20 ns ADC/DACBCLK pulse width low tBCL 20 ns DACLRC/ADCLRC set-up time to ADC/DACBCLK rising edge tLRSU 10 ns DACLRC/ADCLRC hold time from ADC/DACBCLK rising edge tLRH 10 ns DIN set-up time to DACBCLK rising edge tDS 10 ns DIN hold time from DACBCLK rising edge tDH 10 ns DOUT propagation delay from ADCBCLK falling edge tDD 0 10 ns Table 3 Digital Audio Data Timing – Slave Mode Note: ADCLRC and DACLRC should be synchronous with MCLK, although the WM8776 interface is tolerant of phase variations or jitter on these signals. |
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