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X3100PT-V Datasheet(PDF) 3 Page - Xicor Inc. |
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X3100PT-V Datasheet(HTML) 3 Page - Xicor Inc. |
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3 / 40 page  X3100/X3101 – Preliminary Information Characteristics subject to change without notice. 3 of 40 REV 1.1.8 12/10/02 www.xicor.com Cell Voltage Balancing Control (CB1-CB4): These outputs are used to switch external FETs in order to perform cell voltage balancing control. This function can be used to adjust individual cell voltages (e.g. during cell charging). CB1–CB4 can be driven high (Vcc) or low (Vss) to switch external FETs ON/OFF. When using the X3101, the CB4 pin can be left unconnected, or the FET control can be used for other purposes. Current Sense Inputs (VCS1–VCS2): A sense resistor (RSENSE) is connected between VCS1 and VCS2 (Figure 1). RSENSE has a resistance in the order of 20m Ω to 100mΩ, and is used to monitor current flowing through the battery terminals, and protect against over-current conditions. The voltage at each end of RSENSE can also be monitored at pin AO. Over-charge Voltage detect Time control (OVT): This pin is used to control the delay time (TOV) associated with the detection of an over-charge condition (see section “Over-charge Protection” on page 13). Over-discharge detect/release time control (UVT): This pin is used to control the delay times associated with the detection (TUV) and release (TUVR) of an over- discharge (under-voltage) condition (see section “Over- discharge Protection” on page 15). Over-current detect/release time control (OCT): This pin is used to control the delay times associated with the detection (TOC) and release (TOCR) of an over- current condition (see section “Over-Current Protection” on page 18). Analog Output (AO): The analog output pin is used to externally monitor various battery parameter voltages. The voltages which can be monitored at AO (see section “Analog Multiplexer Selection” on page 20) are: – Individual cell voltages – Voltage across the current sense resistor (RSENSE) . This voltage is amplified with a gain set by the user in the control register (see section “Current Monitor Function” on page 20.) The analog select pins pins AS0–AS2 select the desired voltage to be monitored on the AO pin. Analog Output Select (AS0–AS2): These pins select which voltage is to be multiplexed to the output AO (see section “Sleep Control (SLP)” on page 10 and section “Current Monitor Function” on page 20) Serial Input (SI): SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the device are input on this pin. Serial Output (SO): SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. While CS is HIGH, SO will be in a High Impedance state. Note: SI and SO may be tied together to form one line (SI/SO). In this case, all serial data communication with the X3100 or X3101 is undertaken over one I/O line. This is permitted ONLY if no simultaneous read/write operations occur. Serial Clock (SCK): The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS): When CS is HIGH, the device is deselected and the SO output pin is at high impedance. CS LOW enables the SPI serial bus. Over-charge Voltage Protection/Load Monitor (OVP/LMON): This one pin performs two functions depending upon the present mode of operation of the X3100 or X3101. —Over-charge Voltage Protection (OVP) This pin controls the switching of the battery pack charge FET. This power FET is a P-channel device. As such, cell charge is possible when OVP/LMON=VSS, and cell charge is prohibited when OVP/LMON=VCC. In this configuration the X3100 and X3101 turn off the charge voltage when the cells reach the over-charge limit. This prevents damage to the battery cells due to the application of charging voltage for an extended period of time (see section “Over-charge Protection” on page 13). |
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