IS61S6432-133TQ datasheet(11/19 Pages) ISSI | 64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

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IS61S6432-133TQ Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

Part #	IS61S6432-133TQ

Description	64K x 32 SYNCHRONOUS PIPELINE STATIC RAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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Integrated Silicon Solution, Inc. • 1-800-379-4774

11

Rev.B

06/28/01

IS61S6432

ISSI®

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200(1)

-166

-133

-117

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max. Min. Max.

Unit

tKC

Cycle Time

5

—

6

—

7.5

—

8.5

—

ns

tKH

Clock High Time

1.6

—

2.4

—

2.8

—

3

—

ns

tKL

Clock Low Time

1.6

—

2.4

—

2.8

—

3

—

ns

tAS

Address Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tSS

Address Status Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tWS

Write Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tDS

Data In Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tCES

Chip Enable Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tAVS

Address Advance Setup Time

2

—

2.5

—

2.5

—

2.5

—

ns

tAH

Address Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tSH

Address Status Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tDH

Data In Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tWH

Write Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tCEH

Chip Enable Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tAVH

Address Advance Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tCFG(2)

Configuration Setup

25

—

25

—

30

—

35

—

ns

-5

-6

-7

-8

Symbol

Parameter

Min. Max.

Min. Max.

Min. Max. Min. Max.

Unit

tKC

Cycle Time

10

—

12

—

13

—

15

—

ns

tKH

Clock High Time

3.5

—

4

—

6

—

6

—

ns

tKL

Clock Low Time

3.5

—

4

—

6

—

6

—

ns

tAS

Address Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tSS

Address Status Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tWS

Write Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tDS

Data In Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tCES

Chip Enable Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tAVS

Address Advance Setup Time

2.5

—

2.5

—

2.5

—

2.5

—

ns

tAH

Address Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tSH

Address Status Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tDH

Data In Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tWH

Write Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tCEH

Chip Enable Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tAVH

Address Advance Hold Time

0.5

—

0.5

—

0.5

—

0.5

—

ns

tCFG(2)

Configuration Setup

35

—

45

—

52

—

60

—

ns

Note:

1. ADVANCE INFORMATION ONLY.

2. Configuration signal MODE is static and must not change during normal operation.

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