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DS2196L Datasheet(PDF) 5 Page - Dallas Semiconductor

Part # DS2196L
Description  T1 Dual Framer LIU
Download  157 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2196L Datasheet(HTML) 5 Page - Dallas Semiconductor

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LIST OF TABLES
Table 2-1: Pin Description Sorted by Pin Number................................................................................ 10
Table 4-1: Register Map Sorted by Address .......................................................................................... 21
Table 6-1: Output Pin Test Modes .......................................................................................................... 36
Table 6-2: Receive Data Source Mux Modes......................................................................................... 37
Table 6-3: TPOSB/TNEGB Data Source Select..................................................................................... 38
Table 7-1: Receive T1 Level Indication .................................................................................................. 57
Table 7-2: Alarm Criteria ........................................................................................................................ 59
Table 8-1: Line Code Violation Counting Arrangements..................................................................... 66
Table 8-2: Path Code Violation Counting Arrangements..................................................................... 67
Table 8-3: Multiframes Out Of Sync Counting Arrangements............................................................ 67
Table 12-1: Transmit Code Length......................................................................................................... 75
Table 12-2: Receive Code Length ........................................................................................................... 75
Table 15-1: Bert Pattern Select Options................................................................................................. 89
Table 15-2: Repetitive Pattern Length Options..................................................................................... 90
Table 15-3: Bert Rate Insertion Select.................................................................................................... 91
Table 16-1: Error Rate Options .............................................................................................................. 98
Table 16-2: Error Insertion examples..................................................................................................... 99
Table 17-1: Transmit HDLC Configuration .......................................................................................... 99
Table 18-1: HDLC/BOC Controller Register List............................................................................... 102
Table 19-1: Line Build Out Select In LICR ......................................................................................... 119
Table 19-2: Transformer Specifications ............................................................................................... 120
Table 20-1: Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture............................ 128
Table 20-2: ID Code Structure .............................................................................................................. 128
Table 20-3: Device ID Codes.................................................................................................................. 129
Table 20-4: Boundary Scan Register Description................................................................................ 130


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