- 8 -

Rev 2.0

Dec. 2003

K7R323682M

K7R321882M

K7R320982M

READ

DDR READ

WRITE PORT NOP

READ NOP

POWER-UP

WRITE NOP

LOAD NEW

WRITE ADDRESS

LOAD NEW

READ ADDRESS

ALWAYS

(FIXED)

WRITE

STATE DIAGRAM

Notes : 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1.

2. "READ" refers to read active status with R=Low, "READ " refers to read inactive status with R=high. "WRITE" and " WRITE" are the same case.

3. Read and write state machine can be active simulateneously.

4. State machine control timing sequence is controlled by K.

ALWAYS

(FIXED)

READ

WRITE

READ

WRITE

READ

WRITE

DDR WRITE