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ZSSC3136BE1C Datasheet(PDF) 8 Page - Integrated Device Technology |
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ZSSC3136BE1C Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 24 page ZSSC3136 Datasheet © 2016 Integrated Device Technology, Inc. 8 January 22, 2016 No. Parameter Symbol Conditions Min Typ Max Unit 1.3.7. System Response 1.3.7.1 Startup time 1) 3) (To 1 st output, ROM check disabled) tSTARTUP 1-step ADC, fOSC=3MHz rADC=14bit) 35 ms 1.3.7.2 Response time 1) (100% input step; refer to Table 2.2) tRESPONSE 1-step ADC, fOSC=4MHz, rADC=13bit 8.7 13.1 17.4 ms 1.3.7.3 Bandwidth 1) (In comparison to an equivalent analog SSC. Refer to Table 2.2) BW 1-step ADC 200 Hz 1.3.7.4 Analog output noise peak-to-peak 1) VNOISE_PP Shorted inputs bandwidth ≤ 10kHz 10 mV 1.3.7.5 Analog output noise RMS 1) VNOISE_RMS Shorted inputs bandwidth ≤ 10kHz 3 mV 1.3.7.6 Ratiometricity error RE Maximum error for VDDE=5V to 4.5/5.5V 1000 ppm 1.3.7.7 Overall failure Deviation from ideal line including INL, gain, offset and temperature errors. No sensor-caused effects. Failure for digital readout shown in parenthesis. FOVERALL_TQI fOSC ≤3MHz, rADC=13bit, temperature range TAMB_TQI 0.25 (0.1) % FS FOVERALL_TQA fOSC ≤3MHz, rADC=13bit, temperature range TAMB_TQA 0.5 (0.25) % FS FOVERALL_TQE fOSC ≤3MHz, rADC=13bit, temperature range TAMB_TQE 1.0 (0.5) % FS 1) No measurement in mass production, parameter is guaranteed by design and/or quality observation. 2) Minimum output voltage to VDDE or maximum output voltage to VSSE. 3) Depends on resolution and configuration. Start routine begins approximately 0.8ms after power on. |
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