BT730

Datasheet

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Notes:

1. Unused pins may have internal connections and must not be connected.

2. Pins 2, 6, 32, and 33 (SPI related) are only for Laird internal production purposes.

3. Power-on-reset (power cycling and brown out consideration) – The reset circuitry within the BT730

module incorporates a brown-out detector; this may simplify power supply design. The BT730 reset

line is an active low input (Input debounced so must be low for more than 5 ms to cause a reset).

Upon the application of power, the Power On Reset circuit built into the module ensures that the unit

starts correctly. There is no need for an external power reset monitor.

4. Power Supply Consideration – The power supply for the module should be a single voltage source of

VCC within the VCC_IN range of 3.3 V to 5.0 V. It must be able to provide sufficient current in a

transmit burst. This can rise to 200 mA. To limit dissipation it is recommended that you use a voltage

at the lower end of the range.

5. The module includes regulators to provide internal local 3.3 V. This rail is accessible on pin 13 for

monitoring purposes only. Under no circumstances should this pin be used to source current.

2.2.1 COMPATIBILITY NOTE FOR LEGACY DEVICES

If Reset compatibility is required with BTM402 and BTM404: Reset logic must be inverted (on the host PCB), by

using suitable BJT (MMBT3904) with collector connected to Reset pin BT730 module pin 5. A fixed 10k Ohm pull

down resistor to ground (BJT input) then ensures that the BT730 module is out of reset for the condition when

host has yet to control the reset line.

Add a 10 k pull-up to the host PCB on the UART_RX, or the module remains in deep sleep if not driven to high.

Add a 10 k pull-down to the host PCB on the UART_CTS that if it is not connected (which we do not recommend)

then the default state for UART_CTS input will be asserted which means can send data out of UART_TX line.



GPIO lines can be configured through software to be either inputs or outputs with weak or strong pull-ups

or pull-downs. At reset, all GPIO lines are configured as inputs with weak pull-downs.



UART_RX, UART_TX, UART_CTS, UART_RTS, UART_RI, UART_DCD, and UART_DSR are 3.3 V level logic. For

example, when RX and TX are idle they sit at 3.3 V. Conversely, for handshaking pins CTS, RTS, RI, DCD, and

DSR, a 0 V is treated as an assertion.



Pin 28 (UART_RI) is active low. It is normally 3.3 V. When a remote device initiates a connection, this pin

goes low. When this pin is converted to RS232 voltage levels, it has the correct voltage level for assertion.



Pin 17 (UART_DCD) is active low. It is normally 3.3 V. When a connection is live, this pin is low. This means

that when this pin is converted to RS232 voltage levels it has the correct voltage level for assertion.



Pin 16 (UART_DSR) is an input, with active low logic. It should be connected to the DTR output of the host.

When the BTM730 module is in high speed mode (see S Register 507 in the Firmware User manual), this pin

should be asserted by the host to ensure that the connection is maintained. A deassertion means that the

connection should be dropped or an online command mode is being requested.



Pin 13 (VCC_3V3 monitor) may only be used for monitoring (must not be used as a current source).



The GPIO pins can be accessed using S Registers 623 to 629.



GPIO3 is also used for DTR output (active low). See S Register 552 and 553 in the Firmware User manual.



Analogue 0 and 1 should not exceed 1.8 V and S Registers 701 and 702 are used to access them.