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ICS501-DPK Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS501-DPK Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 6 page ICS501B MDS 501B C 1 Revision 120704 Integrat ed Circuit Systems ● 5 25 Race Stre et, San Jo se, CA 9 5126 ● te l (40 8 ) 2 97-12 01 ● www.ics t.co m LOCO™ PLL CLOCK MULTIPLIER Description The ICS501B LOCOTM is the most cost effective way to generate a high-quality clock output from a lower frequency crystal or clock input. The name LOCO stands for Low Cost Oscillator, as it is designed to replace crystal oscillators in most electronic systems. Using Phase-Locked Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 20 MHz. Stored in the chip’s ROM is the ability to generate nine different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). The device also has an output enable pin which tri-states the clock output when the OE pin is taken low. This product is intended for clock generation. It has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. For applications which require defined input to output skew, use the ICS570B. Features • Packaged as 8 pin SOIC or die • Available in Pb (lead) free package • ICS’ lowest cost PLL clock • Zero ppm multiplication error • Input crystal frequency of 5 MHz • Input clock frequency of 5 MHz • Output clock frequencies up to 15 MHz • Extremely low jitter of 25 ps (one sigma) • Compatible with popular CPUs • Duty cycle of 45/55 up to 20 MHz • Nine selectable frequencies • Operating voltage of 3.3 V or 5.5 V • Tri-state output for board level testing • 25 mA drive capability at TTL levels • Ideal for oscillator replacement • Industrial temperature version available • Advanced, low-power CMOS process Block Diagram CLK PLL Clock M ultiplier Circuitry and ROM Crystal or Clock input GND OE VDD Crystal O scillator S1:0 X1/ICLK X2 O ptional crystal capacitors 2 |
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