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MC9S08RD60 Datasheet(PDF) 9 Page - Motorola, Inc

Part # MC9S08RD60
Description  Microcontrollers
Download  232 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MC9S08RD60 Datasheet(HTML) 9 Page - Motorola, Inc

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SoC Guide — MC9S08RG60/D Rev 1.10
Freescale Semiconductor
9
MC9S08RC/RD/RE/RG
5.7
Real-Time Interrupt (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.8
Reset, Interrupt, and System Control Registers and Control Bits . . . . . . . . . . . . . . 64
5.8.1
Interrupt Pin Request Status and Control Register (IRQSC) . . . . . . . . . . . . . . . . 64
5.8.2
System Reset Status Register (SRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.8.3
System Background Debug Force Reset Register (SBDFR) . . . . . . . . . . . . . . . . 67
5.8.4
System Options Register (SOPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.8.5
System Device Identification Register (SDIDH, SDIDL) . . . . . . . . . . . . . . . . . . . 69
5.8.6
System Real-Time Interrupt Status and Control Register (SRTISC) . . . . . . . . . . 69
5.8.7
System Power Management Status and Control 1 Register (SPMSC1) . . . . . . . 71
5.8.8
System Power Management Status and Control 2 Register (SPMSC2) . . . . . . . 72
Chapter 6 Central Processor Unit (CPU)
6.1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3
Programmer’s Model and CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.1
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.2
Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.3
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.4
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.5
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.4
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4.1
Inherent Addressing Mode (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4.2
Relative Addressing Mode (REL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4.3
Immediate Addressing Mode (IMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4.4
Direct Addressing Mode (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.4.5
Extended Addressing Mode (EXT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.4.6
Indexed Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.5
Special Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.5.1
Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.5.2
Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.5.3
Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.5.4
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.5.5
BGND Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.6
HCS08 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82


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