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ACPL-33JT Datasheet(PDF) 9 Page - Broadcom Corporation. |
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ACPL-33JT Datasheet(HTML) 9 Page - Broadcom Corporation. |
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9 / 36 page  Broadcom - 9 - ACPL-33JT Data Sheet Electrical Specifications VCC2 to UVLO High Delay tPLH_UVLO 9 20 μs 30 o VCC2 to UVLO Low Delay tPHL_UVLO 720 μs 30 p VCC2 UVLO to VOUT High Delay tUVLO_ON 56.5 μs 30 q VCC2 UVLO to VOUT Low Delay tUVLO_OFF 1.1 2 μs 30 r Desaturation Protection Desat Sensing Threshold VDESAT 6.65 7.0 7.35 V 18 Desat Charging Current ICHG 0.8 1.0 1.2 mA VDESAT = 0V, VDESAT =6V 19 Desat Discharging Current IDSCHG 19 60 106 mA VDESAT = 7.5V 20 Desat Blanking Time tDESAT(BLANKING) 0.3 0.6 0.9 μs RSSD = 0 Cg= 10 nF 30 s Desat Sense to 90% VGATE Delay tDESAT(90%) 0.05 0.2 0.5 μs 22, 30 t Desat Sense to 10% VGATE Delay tDESAT(10%) 0.5 1.2 2 μs 22, 30 u Desat to Low Level FAULT Signal Delay tDESAT(FAULT) 4.4 8 μs v Output Mute Time due to Desaturation tDESAT(MUTE) 37.5 12 ms 30 w Time Input Kept Low Before Fault Reset to High tDESAT(RESET) 37.5 12 ms 30 x a. PWM switching frequency of primary gate drive (PGD) is dithered in a range of ±6% typically over 3.3 ms. b. CIN is measured between pin 7 and pin 8 of the IC. c. Maximum pulse width=1 μs, maximum duty cycle=1%. d. Maximum pulse width = 1.0 ms, maximum duty cycle = 1%. e. Once VOH of ACPL-33JT is allowed to go high (VCC2 – VEE2 > VUVLO), the DESAT detection features of the ACPL-33JT will be the primary source of IGBT protection. Once VCC2 exceeds VUVLO+ threshold, DESAT will remain functional until VCC2 is below VUVLO- threshold. Thus, the DESAT detection and UVLO features of the ACPL-33JT work in conjunction to ensure constant IGBT protection. f. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output. g. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output. h. Pulse Width Distortion (PWD) is defined as (tPHL – tPLH) of any given unit. i. As measured from IF to VO. j. Dead Time Distortion (DTD) is defined as (tPLH – tPHL) between any two ACPL-33JT under the same test conditions. k. Common mode transient immunity in the output high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output remains in the high state (that is, VO > 14V). CMH specification is guaranteed by design and not subjected to production test. l. Common mode transient immunity in the output low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to ensure that the output remains in the low state (that is, VO < 2.0V). CML specification is guaranteed by design and not subjected to production test. m. This is the “increasing” (that is, turn-on or “positive going” direction) of VCC2 – VEE2. n. This is the “decreasing” (that is, turn-off or “negative going” direction) of VCC2 – VEE2. o. The delay time when VCC2 exceeded UVLO+ threshold to 50% of /UVLO positive going edge. p. The delay time when VCC2 exceeded UVLO- threshold to 50% of /UVLO negative going edge. q. The delay time when VCC2 exceeded UVLO+ threshold to 50% of High level output. r. The delay time when VCC2 exceeded UVLO- threshold to 50% of Low level output. s. The delay time for ACPL-33JT to respond to a DESAT fault condition without any external DESAT capacitor. t. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions. u. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions. v. The amount of time from when DESAT threshold is exceeded to /Fault output Low – 50% of VCC1 voltage. w. The amount of time when DESAT threshold is exceeded, Output is mute to LED input. x. The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High. Table 8 Electrical Specifications (Continued) Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note |
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