5

DRV3220-Q1

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SLVSDM3 – FEBRUARY 2017

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Copyright © 2017, Texas Instruments Incorporated

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to network ground terminal, unless specified otherwise.

(3)

in Recommended Operating Conditions.

(4)

The maximum value also depends on PCB thermal design, modulation scheme, and motor operation time.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

POS

MIN

MAX

UNIT

2.1

DC voltage

VS, VSH

–0.3

60

V

2.1a

VS

Negative voltages with minimum serial resistor 5 Ω,

–5

V

2.1c

Negative voltages with minimum serial resistor 5 Ω,

–2.5

V

2.1b

VSH

Negative voltages with minimum serial resistor 10 Ω,

–5

V

2.1d

Negative voltages with minimum serial resistor 10 Ω,

–2.5

V

2.2A

Gate high-side voltage

GHSx

–9

70

V

2.2B

Source high-side voltage

SHSx

–9

70

V

2.3

Gate-source high-side voltage

difference

GHSx-

SHSx

Externally driven, internal limited, see position 5.4 in

Electrical Characteristics

–0.3

15

V

2.4

Gate low-side voltage

GLSx

–9

20

V

2.5

Source low-side voltage

SLSx

–9

7

V

2.6

Gate-source low-side voltage

difference

GLSx-

SLSx

Externally driven, internal limited, see position 5.5 in

Electrical Characteristics

–0.3

15

V

2.7

Boost converter

BOOST, SW

–0.3

70

V

2.9

Analog input voltage

VDDIO

–0.3

60

V

2.9a

ADREF

–0.3

60

V

2.11

RVSET

–0.3

60

V

2.10

Digital input voltage

ILSx,IHSx, EN, DRVOFF, SCLK, NCS, SDI

–0.3

60

V

2.13

Difference between GNDA and

GNDLS_B

GNDA, GNDLS_B

–0.3

0.3

V

2.20

–250

250

V/µs

2.21

Analog and digital output

voltages

ERR, SDO, RO

–0.3

6

V

2.22

Unused pins (connect to GND)

TEST

–0.3

0.3

V

2.24

Internal supply voltage

VCC5

–0.3

6

V

2.25

VCC3

–0.3

3.6

V

2.21

A

Forced input and output current

ERR, SDO, RO

–10

10

mA

2.24

A

(3)

Internal current limit

80

mA

2.26

Limited by VCC5

80

mA

2.27

Driver FET total gate charge (per

nC

2.28

nC