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MPC9600 Datasheet(PDF) 5 Page - Motorola, Inc |
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MPC9600 Datasheet(HTML) 5 Page - Motorola, Inc |
5 / 16 page TIMING SOLUTIONS 5 MOTOROLA Table 4: DC CHARACTERISTICS (VCC = 2.5 V ±5%, TA = –40° to +85°C) Symbol Characteristics Min Typ Max Unit Condition VIH Input High Voltage 1.7 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.7 V LVCMOS VPP Peak-to-peak input voltage (DC) PCLK, PCLK 250 mV LVPECL VCMRa Common Mode Range (DC) PCLK, PCLK 1.0 VCC-0.6 V LVPECL VOH Output High Voltage 1.8 V IOH=-15 mAb VOL Output Low Voltage 0.6 V IOL= 15 mA ZOUT Output Impedance 17 – 20 W IIN Input Leakage Current ±150 µA VIN = VCC or GND ICCA Maximum PLL Supply Current 3.0 5.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9600 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per output. Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a Symbol Characteristics Min Typ Max Unit Condition fref Input Frequency B8 feedback (FSEL_FB=0) B12 feedback (FSEL_FB=1) Static test mode (VCCA = GND) 25 16.67 0 50 33 500 MHz MHz MHz PLL locked PLL locked VCCA = GND fVCO VCO Frequency 200 400 MHz fMAX Maximum Output Frequency B2 outputs (FSELx=0) B4 outputs (FSELx=1) 100 50 200 100 MHz MHz PLL locked PLL locked frefDC Reference Input Duty Cycle 25 75 % VPP Peak-to-peak Input Voltage PCLK, PCLK 500 1000 mV LVPECL VCMRb Common Mode Range PCLK, PCLK (VCC = 3.3 V ±5%) PCLK, PCLK (VCC = 2.5 V ±5%) 1.2 1.2 VCC-0.8 VCC-0.6 V V LVPECL LVPECL tr, tf CCLK Input Rise/Fall Time 1.0 ns see Figure 12 t( ∅) Propagation Delay (static phase offset) CCLK to FB_IN PECL_CLK to FB_IN –60 +30 +40 +130 +140 +230 ps ps PLL locked PLL locked tsk(o) Output-to-output Skew all outputs, single frequency all outputs, multiple frequency within QAx output bank within QBx outputs within QCx outputs 70 70 30 40 30 150 150 75 125 75 ps ps ps ps ps Measured at coincident rising edge DC Output Duty Cycle 45 50 55 % tr, tf Output Rise/Fall Time 0.1 1.0 ns see Figure 12 tPLZ, HZ Output Disable Time 10 ns tPZL, ZH Output Enable Time 10 ns BW PLL Closed Loop Bandwidth B8 feedback (FSEL_FB=0) B12 feedback (FSEL_FB=1) 1.0 – 10 0.6 – 4.0 MHz MHz –3 dB point of PLL transfer characteristic Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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Similar Description - MPC9600 |
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