f

D

L

V

I

IN

L

×

=

I

= I

VALLEY

LIM

IL

f

Rectifier

Current

Inductorr

Current

Increased

Load Current

Current Limit

Threshold

IN

L

V

D

I =

L

f

D

g

IN

OUT

V

D

1

V

h

=

-

g

-

D

g

OUT(CL)

VALLEY

L

1

I

= (1 D)

(I

+

I )

2

9

TPS61256C

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SLVSDQ1 – FEBRUARY 2017

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Copyright © 2017, Texas Instruments Incorporated

9.3 Feature Description

9.3.1 Current Limit Operation

The TPS61256xC device employs a valley current limit sensing scheme. Current limit detection occurs during the

off-time by sensing of the voltage drop across the synchronous rectifier.

The output voltage is reduced as the power stage of the device operates in a constant current mode. The

Equation 1.

(1)

The duty cycle (D) can be estimated by Equation 2

(2)

(3)

increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the

current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).

When the current limit is reached the output voltage decreases during further load increase.

Figure 8 illustrates the inductor and rectifier current waveforms during current limit operation.

Figure 8. Inductor/Rectifier Currents in Current Limit Operation

9.3.2 Enable

The TPS61256xC device starts operation when EN is set high and starts up with the soft-start sequence. For

proper operation, the EN pin must be terminated and must not be left floating.

Pulling the EN low and Vin above UVLO, the device is in the forced pass-through mode and the output voltage

follows the input voltage (with a voltage drop of the inductor DCR and Rdson of HS FET).

9.3.3 Softstart

The TPS61256xC device has an internal softstart circuit that limits the inrush current during start-up. The first

step in the start-up cycle is the pre-charge phase. During pre-charge, the rectifying switch is turned on until the

output capacitor is charged to a value close to the input voltage. The rectifying switch is current limited (500 mA

min.) during this phase. This mechanism is used to limit the output current under short-circuit condition.