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AT43USB370E-AC Datasheet(PDF) 8 Page - ATMEL Corporation |
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AT43USB370E-AC Datasheet(HTML) 8 Page - ATMEL Corporation |
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8 / 50 page  8 AT43USB370 3340B–USB–12/03 A subset of the Control and Status register set, the System Processor Interface registers, is accessible by the system processor as external memory locations. It is used to facilitate data exchange between the system processor and the AT43USB370. System Processor Interface The system processor interface provides 32-bit bi-directional data paths to the external pro- cessor for read and write operations to the AT43USB370's System Interface registers and FIFO. The AT43USB370 appears as a memory mapped peripheral to the external system pro- cessor. The interface logic requires a number of control lines and an 8-bit address bus. DMA The DMA engine provides DMA support for the system processor to transfer data between the processor's memory and the AT43USB370's internal FIFO. The system processor's DMA con- troller controls the DMA operation through standard DMA Request and Acknowledgement signals. The AT43USB370 can only operate as a DMA slave. Oscillator and PLL XTAL1 and XTAL2 are the clock pins to the AT43USB370. An external oscillator or a crystal can be connected to these pins. All clock signals required to operate the AT43USB370 are derived from the on-chip PLL. The on-chip PLL is of a special, low-drive type, designed to operate with most of the 6-Mhz crystals without any external components. The crystal must be of the parallel resonance type requiring a load capacitance of about 10 pF. If the crystal requires a higher value capacitance, external capacitors can be added to the two terminals of the crystal and ground to meet the required value. To assure a quick start-up, a crystal with a high Q, or low ESR, should be used. The 48-MHz clock can also be externally sourced. In this case, the clock source is connected to XTAL1 pin with XTAL2 pin left open and the CLK_SEL pin tied to logic “1”. For proper operation of the PLL, an external RC filter consisting of a series RC network of 470 Ω and 22 nF in parallel with a 2.2 nF capacitor must be connected from the LFT pin to V SS. Only high-quality ceramic capacitors are recommended. Figure 3 shows the required crystal and external circuitry. Figure 3. Oscillator and PLL AT43USB370 XTAL1 XTAL2 6 MHz R1 470 C1 22 nF C2 2.2 nF LFT |
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