COP87L84EGM-XE datasheet(8/42 Pages) NSC

Part #	COP87L84EGM-XE

Description	8-Bit Microcontroller with UART and Three Multi-Function Timers

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Manufacturer	NSC [National Semiconductor (TI)]

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Data Memory Segment RAM Extension

Data memory address 0FF is used as a memory mapped

location for the Data Segment Address Register (S)

The data store memory is either addressed directly by a

single byte address within the instruction or indirectly rela-

tive to the reference of the B X or SP pointers (each con-

tains a single-byte address) This single-byte address allows

an addressing range of 256 locations from 00 to FF hex

The upper bit of this single-byte address divides the data

store memory into two separate sections as outlined previ-

ously With the exception of the RAM register memory from

address locations 00F0 to 00FF all RAM memory is memo-

ry mapped with the upper bit of the single-byte address be-

ing equal to zero This allows the upper bit of the single-byte

address to determine whether or not the base address

range (from 0000 to 00FF) is extended If this upper bit

equals one (representing address range 0080 to 00FF)

then address extension does not take place Alternatively if

this upper bit equals zero then the data segment extension

register S is used to extend the base address range (from

0000 to 007F) from XX00 to XX7F where XX represents the

8 bits from the S register Thus the 128-byte data segment

extensions are located from addresses 0100 to 017F for

data segment 1 0200 to 027F for data segment 2 etc up

to FF00 to FF7F for data segment 255 The base address

range from 0000 to 007F represents data segment 0

Figure 4 illustrates how the S register data memory exten-

sion is used in extending the lower half of the base address

range (00 to 7F hex) into 256 data segments of 128 bytes

each with a total addressing range of 32 kbytes from XX00

to XX7F This organization allows a total of 256 data seg-

ments of 128 bytes each with an additional upper base seg-

ment of 128 bytes Furthermore all addressing modes are

available for all data segments The S register must be

changed under program control to move from one data seg-

ment (128 bytes) to another However the upper base seg-

ment (containing the 16 memory registers IO registers

control registers etc) is always available regardless of the

contents of the S register since the upper base segment

(address range 0080 to 00FF) is independent of data seg-

ment extension

The instructions that utilize the stack pointer (SP) always

reference the stack as part of the base segment (Segment

0) regardless of the contents of the S register The S regis-

ter is not changed by these instructions Consequently the

stack (used with subroutine linkage and interrupts) is always

located in the base segment The stack pointer will be inti-

tialized to point at data memory location 006F as a result of

reset

The 128 bytes of RAM contained in the base segment are

split between the lower and upper base segments The first

116 bytes of RAM are resident from address 0000 to 006F

in the lower base segment while the remaining 16 bytes of

RAM represent the 16 data memory registers located at ad-

dresses 00F0 to 00FF of the upper base segment No RAM

is located at the upper sixteen addresses (0070 to 007F) of

the lower base segment

Additional RAM beyond these initial 128 bytes however will

always be memory mapped in groups of 128 bytes (or less)

at the data segment address extensions (XX00 to XX7F) of

the lower base segment The additional 64 bytes of RAM

(beyond the initial 128 bytes) are memory mapped at ad-

dress locations 0100 to 013F hex

TLDD9765 – 9

Reads as all ones

FIGURE 4 RAM Organization

Reset

The RESET input when pulled low initializes the microcon-

troller Initialization will occur whenever the RESET input is

pulled low Upon initialization the data and configuration

registers for ports L G and C are cleared resulting in these

Ports being initialized to the TRI-STATE mode Pin G1 of the

G Port is an exception (as noted below) since pin G1 is

dedicated as the WATCHDOG andor Clock Monitor error

output pin Port D is set high The PC PSW ICNTRL

CNTRL T2CNTRL and T3CNTRL control registers are

cleared The UART registers PSR ENU (except that TBMT

bit is set) ENUR and ENUI are cleared The Comparator

Select Register is cleared The S register is initialized to

zero The Multi-Input Wakeup registers WKEN WKEDG and

WKPND are cleared The stack pointer SP is initialized to

6F Hex

The device comes out of reset with both the WATCHDOG

logic and the Clock Monitor detector armed

with the

WATCHDOG service window bits set and the Clock Monitor

bit set The WATCHDOG and Clock Monitor circuits are in-

hibited during reset The WATCHDOG service window bits

being initialized high default to the maximum WATCHDOG

service window of 64k tC clock cycles The Clock Monitor bit

being initialized high will cause a Clock Monitor error follow-

ing reset if the clock has not reached the minimum specified

frequency at the termination of reset A Clock Monitor error

will cause an active low error output on pin G1 This error

output will continue until 16 tC–32 tC clock cycles following

the clock frequency reaching the minimum specified value

at which time the G1 output will enter the TRI-STATE mode

The external RC network shown in

Figure 5 should be used

to ensure that the RESET pin is held low until the power

supply to the chip stabilizes

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COP87L84EGM-XE Datasheet(PDF) 8 Page - National Semiconductor (TI)

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