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CAT64LC40JITE13 Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT64LC40JITE13 Datasheet(HTML) 7 Page - Catalyst Semiconductor |
7 / 12 page Discontinued Parts 7 CAT64LC10/20/40 Doc. No. 1021, Rev. C a 16-bit data field is also required following the 8-bit address field. The CAT64LC10/20/40 requires an active LOW CS in order to be selected. Each instruction must be preceded by a HIGH-to-LOW transition of CS before the input of the 4-bit start sequence. Prior to the 4-bit start sequence (1010), the device will ignore inputs of all other logical sequence. Figure 4. Write Instruction Timing Figure 5. Ready/ BUSY BUSY BUSY BUSY BUSY Status Instruction Timing Read Upon receiving a READ command and address (clocked into the DI pin), the DO pin will output data one tPD after the falling edge of the 16th clock (the last bit of the address field). The READ operation is not affected by the RESET input. Write After receiving a WRITE op code, address and data, the device goes into the AUTO-Clear cycle and then the * Please check instruction set table for address SK DI CS DO RESET 10100100 ADDRESS* D15 D0 RDY/ BUSY SK DI CS DO RESET WRITE INSTRUCTION NEXT INSTRUCTION HIGH LOW RDY/ BUSY |
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