Philips Semiconductors

Product data

SCC2681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

6

AC CHARACTERISTICS

SYMBOL

PARAMETER

LIMITS

UNIT

SYMBOL

PARAMETER

Min

Typ

Max

UNIT

Reset Timing (Figure 3)

RESET pulse width

200

–

–

ns

A0-A3 set-up time to RDN, WRN LOW

10

–

–

ns

A0-A3 hold time from RDN, WRN LOW

100

–

–

ns

CEN set-up time to RDN, WRN LOW

0

–

–

ns

CEN hold time from RDN, WRN HIGH

0

–

–

ns

WRN, RDN pulse width

225

–

–

ns

Data valid after RDN LOW

–

–

175

ns

Data bus floating after RDN HIGH

–

–

100

ns

Data set-up time before WRN HIGH

100

–

–

ns

Data hold time after WRN HIGH

20

–

–

ns

200

–

–

ns

Port input set-up time before RDN LOW

0

–

–

ns

Port input hold time after RDN HIGH

0

–

–

ns

Port output valid after WRN HIGH

–

–

400

ns

Interrupt Timing (Figure 6)

INTRN (or OP3-OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt)

–

–

300

ns

Write THR (TxRDY interrupt)

–

–

300

ns

Reset command (delta break interrupt)

–

–

300

ns

Stop C/T command (counter interrupt)

–

–

300

ns

Read IPCR (input port change interrupt)

–

–

300

ns

Write IMR (clear of interrupt mask bit)

–

–

300

ns

X1/CLK HIGH or LOW time

100

–

–

ns

X1/CLK frequency

1.0

3.6864

4.0

MHz

CTCLK (IP2) HIGH or LOW time

100

–

–

ns

CTCLK (IP2) frequency

0

–

4.0

MHz

RxC HIGH or LOW time

220

–

–

ns

RxC frequency (16

×)

(1

×)

0

0

–

–

2.0

1.0

MHz

MHz

TxC HIGH or LOW time

220

–

–

ns

TxC frequency (16

×)

(1

×)

0

0

–

–

2.0

1.0

MHz

MHz

Transmitter Timing (Figure 8)

TxD output delay from TxC external clock input on IP pin

–

–

350

ns

Output delay from TxC LOW at OP pin to TxD data output

0

–

150

ns

Receiver Timing (Figure 10)

RxD data setup time before RxC HIGH at external clock input on IP pin

240

–

–

ns

RxD data hold time after RxC HIGH at external clock input on IP pin

200

–

–

ns

NOTES:

1. For operating at elevated temperatures, the device must be derated based on +150

°C maximum junction temperature.

2. Parameters are valid over specified temperature range.

3. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4 V and 2.4 V with a

transition time of

≤ 20 ns. For X1/CLK this swing is between 0.4 V and 4.4 V. All time measurements are referenced at input voltages of

0.8 V and 2.0 V as appropriate.

4. Typical values are at +25

°C, typical supply voltages, and typical processing parameters.

6. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this

case, all timing specifications apply referenced to the falling and rising edges of CEN, CEN and RDN (also CEN and WRN) are ANDed

internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the cycle.

7. If CEN is used as the ‘strobing’ input, the parameter defines the minimum HIGH times between one CEN and the next. The RDN signal must