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SCC2681AE1N40 Datasheet(PDF) 9 Page - NXP Semiconductors |
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SCC2681AE1N40 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 29 page  Philips Semiconductors Product data SCC2681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 9 Output Port The output port pins may be controlled by the OPR, OPCR, MR and CR registers. Via appropriate programming they may be just another parallel port to external circuits, or they may represent many internal conditions of the UART. When this 8-bit port is used as a general purpose output port, the output port pins drive a state which is the complement of the Output Port Register (OPR). OPR(n) = 1 results in OP(n) = LOW and vice versa. Bits of the OPR can be individually set and reset. A bit is set by performing a write operation at address 0xE with the accompanying data specifying the bits to be set (1 = set, 0 = no change). Likewise, a bit is reset by a write at address 0xF with the accompanying data specifying the bits to be reset (1 = reset, 0 = no change). Outputs can be also individually assigned specific functions by appropriate programming of the Channel A mode registers (MR1A, MR2A), the Channel B mode registers (MR1B, MR2B), and the Output Port Configuration Register (OPCR). Please note that these pins drive both HIGH and LOW. However when they are programmed to represent interrupt type functions (such as receiver ready, transmitter ready, DMA signals or counter/timer ready) they will be switched to an open drain configuration in which case an external pull-up device would be required. TRANSMITTER OPERATION The SCC2681 is conditioned to transmit data when the transmitter is enabled through the command register. The SCC2681 indicates to the CPU that it is ready to accept a character by setting the TxRDY bit in the status register. This condition can be programmed to generate an interrupt request at OP6 or OP7 and INTRN. When a character is loaded into the Transmit Holding Register (THR), the above conditions are negated. Data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. The TxRDY conditions are then asserted again which means one full character time of buffering is provided. Characters cannot be loaded into the THR while the transmitter is disabled. The transmitter converts the parallel data from the CPU to a serial bit stream on the TxD output pin. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is sent first. Following the transmission of the stop bits, if a new character is not available in the THR, the TxD output remains HIGH and the TxEMT bit in the Status Register (SR) will be set to 1. Transmission resumes and the TxEMT bit is cleared when the CPU loads a new character into the THR. If the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. The transmitter can be forced to send a continuous LOW condition by issuing a send break command. The transmitter can be reset through a software command (0x30). If it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. If CTS operation is enable, the CTSN input must be LOW in order for the character to be transmitted. If it goes HIGH in the middle of a transmission, the character in the shift register is transmitted and TxDA then remains in the marking state until CTSN goes LOW. The transmitter can also control the deactivation of the RTSN output. If programmed, the RTSN output will be reset one bit time after the character in the transmit shift register and transmit holding register (if any) are completely transmitted, if the transmitter has been disabled. Receiver The SCC2681 is conditioned to receive data when enabled through the command register. The receiver looks for a HIGH-to-LOW (mark-to-space) transition of the start bit on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled each 16 × clock for 7 1/2 clocks (16 × clock mode) or at the next rising edge of the bit time clock (1 × clock mode). If RxD is sampled HIGH, the start bit is invalid and the search for a valid start bit begins again. If RxD is still LOW, a valid start bit is assumed and the receiver continues to sample the input at one bit time intervals at the theoretical center of the bit, until the proper number of data bits and parity bit (if any) have been assembled, and one stop bit has been detected. The least significant bit is received first. The data is then transferred to the Receive Holding Register (RHR) and the RxRDY bit in the SR is set to a 1. This condition can be programmed to generate an interrupt at OP4 or OP5 and INTRN. If the character length is less than eight bits, the most significant unused bits in the RHR are set to zero. After the stop bit is detected, the receiver will immediately look for the next start bit. However, if a non-zero character was received without a stop bit (framing error) and RxD remains LOW for one half of the bit period after the stop bit was sampled, then the receiver operates as if a new start bit transition had been detected at that point (one-half bit time after the stop bit was sampled). The parity error, framing error, overrun error and received break state (if any) are strobed into the SR at the received character boundary, before the RxRDY status bit is set. If a break condition is detected (RxD is LOW for the entire character including the stop bit), a character consisting of all zeros will be loaded into the RHR and the received break bit in the SR is set to 1. The RxD input must return to HIGH for two (2) clock edges of the X1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. This will usually require a HIGH time of one X1 clock period or 3 X1 edges since the clock of the controller is not synchronous to the X1 clock. Receiver FIFO The RHR consists of a First-In-First-Out (FIFO) stack with a capacity of three characters. Data is loaded from the receive shift register into the top most empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all three stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the RHR outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits (see below) are ‘popped’ thus emptying a FIFO position for new data. Receiver Status Bits In addition to the data word, three status bits (parity error, framing error, and received break) are also appended to each data character in the FIFO (overrun is not). Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the ‘character’ mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the ‘block’ mode, the status provided in the SR for these three bits is the logical-OR of the status for all characters coming to the top of the FIFO since the last ‘reset error’ command was issued. In either mode reading the SR does not affect the FIFO. The FIFO is ‘popped’ only when the RHR is read. Therefore the status register should be read prior to reading the FIFO. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the |
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