MB85RS2MT

2

DS501-00023-0v01-E

■ PIN ASSIGNMENT

■ PIN FUNCTIONAL DESCRIPTIONS

Pin No. Pin Name

Functional description

1CS

Chip Select pin

This is an input pin to make chips select. When CS is “H” level, device is in deselect

(standby) status and SO becomes High-Z. Inputs from other pins are ignored for this

time. When CS is “L” level, device is in select (active) status. CS has to be “L” level before

inputting op-code.

3WP

Write Protect pin

This is a pin to control writing to a status register. The writing of status register (see “

■

STATUS REGISTER”) is protected in related with WP and WPEN. See “

■ WRITING

PROTECT” for detail.

7HOLD

Hold pin

This pin is used to interrupt serial input/output without making chips deselect. When

HOLD is “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become

do not care. While the hold operation, CS has to be retained “L” level.

6SCK

Serial Clock pin

This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising

edge, SO is output synchronously to a falling edge.

5SI

Serial Data Input pin

This is an input pin of serial data. This inputs op-code, address, and writing data.

2SO

Serial Data Output pin

This is an output pin of serial data. Reading data of FRAM memory cell array and status

register data are output. This is High-Z during standby.

8

VDD

Supply Voltage pin

4

VSS

Ground pin

1

2

3

4

8

7

6

5

CS

WP

SO

VSS

VDD

SCK

SI

HOLD

1

2

3

4

8

7

6

5

CS

WP

SO

VSS

VDD

SCK

SI

HOLD

(TOP VIEW)

(DIP-8P-M03)

(TOP VIEW)

(FPT-8P-M08)