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TFP410 Datasheet(PDF) 8 Page - Texas Instruments |
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TFP410 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 26 page  TFP410 TI PanelBus DIGITAL TRANSMITTER SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing diagrams tr tf 80% VOD 20% VOD DVI Outputs Figure 1. Rise and Fall Time for DVI Outputs th(IDF) tsu(IDF) th(IDR) tsu(IDR) VIH VIL IDCK+ DATA[23:0], DE, HSYNC, VSYNC IDCK– Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK ± tsu(ID) th(ID) VIH VIL IDCK+ DATA[23:0], DE, HSYNC, VSYNC th(ID) tsu(ID) Figure 3. Dual Edge Data Setup/Hold Times to IDCK+ tsk(D) 50% TX+ TX– Figure 4. Analog Output Intra-Pair ± Differential Skew tsk(CC) 50% 50% TXN TXM Figure 5. Analog Output Channel-to-Channel Skew |
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