K4S51153LF - Y(P)C/L/F

September 2004

8

Mobile SDRAM

NOTES :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Parameter

Symbol

-75

-1H

-1L

Unit

Note

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS latency=3

7.5

1000

9.0

1000

9.0

1000

ns

1

CLK cycle time

CAS latency=2

9.0

9.0

12

CLK cycle time

CAS latency=1

-

-

25

CLK to valid output delay

CAS latency=3

5.4

7

7

ns

1,2

CLK to valid output delay

CAS latency=2

7

7

8

CLK to valid output delay

CAS latency=1

-

-

20

Output data hold time

CAS latency=3

2.5

2.5

2.5

ns

2

Output data hold time

CAS latency=2

2.5

2.5

2.5

Output data hold time

CAS latency=1

-

-

2.5

CLK high pulse width

2.5

3.0

3.0

ns

3

CLK low pulse width

2.5

3.0

3.0

ns

3

Input setup time

2.0

2.5

2.5

ns

3

Input hold time

1.0

1.5

1.5

ns

3

CLK to output in Low-Z

1

1

1

ns

2

CLK to output in Hi-Z

CAS latency=3

5.4

7

7

ns

CAS latency=2

7

7

8

CAS latency=1

-

-

20