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UT8CR512K32-17VWC Datasheet(PDF) 9 Page - Aeroflex Circuit Technology |
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UT8CR512K32-17VWC Datasheet(HTML) 9 Page - Aeroflex Circuit Technology |
9 / 16 page 9 Assumptions: 1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be in three-state for the entire cycle. Wn tAVWL Figure 4a. SRAM Write Cycle 1: Write Enable - Controlled Access A(18:0) Qn(7:0) En Dn(7:0) APPLIED DATA tDVWH tWHDX tETWH tWLWH tWHAX tWHQX tWLQZ tAVWH tWHWL |
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