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WM8521HCGED Datasheet(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8521HCGED Datasheet(HTML) 8 Page - Wolfson Microelectronics plc |
8 / 20 page WM8521 Product Preview w PP Rev 1.3 December 2004 8 MASTER CLOCK TIMING MCLK t MCLKL t MCLKH t MCLKY Figure 1 Master Clock Timing Requirements Test Conditions AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT System Clock Timing Information MCLK Master clock pulse width high tMCLKH 11 ns MCLK Master clock pulse width low tMCLKL 11 ns MCLK Master clock cycle time tMCLKY 28 ns MCLK Duty cycle 40:60 60:40 Time from MCLK stopping to digital reset 1.5 12 µs DIGITAL AUDIO INTERFACE Figure 2 Digital Audio Data Timing Test Conditions AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 10 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DIN set-up time to BCLK rising edge tDS 10 ns DIN hold time from BCLK rising edge tDH 10 ns BCLK LRCLK t BCH t BCL t BCY DIN t LRSU t DS t LRH t DH |
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