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WTS701EF Datasheet(PDF) 9 Page - Winbond |
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WTS701EF Datasheet(HTML) 9 Page - Winbond |
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9 / 77 page  WTS701 Publication Release Date: May 2003 - 9 - Revision 3.09 6. PIN DESCRIPTION Table 1. WTS701 Pin Signal Assignment. PIN NO. SYMBOL I/O FUNCTION 2,36,44 VSSA G Analog Ground pins. 3 VCLK I CODEC master clock 4 VFS I CODEC frame synchronization signal 5 VDX O CODEC data output. This pin puts data out in the linear PCM unsigned or 2’s complement format. It is tri-stated until the user requests a CONVERT operation. 6 MISO O SPI Master In, Slave Out pin. Serial data line used to communicate with SPI master. Pin is tri-state when SS =1. 7 XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. 8 XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. The clock to the WTS701 processor is configured by a clock configuration register, which is set by the host processor during the initialization phase. 9,10 VSSD G Digital Ground pin. 11,12 VCCD P Positive Digital Voltage Supply pin. These pins carry noise generated by internal clocks in the chip. They must be independently bypassed to Digital Ground to ensure correct device operation and not connected together. 13 INT O Interrupt Output; an open drain output that indicates that the device wishes an interrupt service. The device can request an interrupt when it finishes an operation or needs more data to process. Under what conditions the device generates an interrupt can be configured through the user configuration registers. This pin remains LOW until a Read Interrupt command is executed. 14 MOSI I SPI Master Out, Slave In. Serial data input from Master and Open Drain 15 SS I SPI Slave Select input. This is an active LOW input used to select the device to respond to an SPI transaction. 16 SCLK I SPI Serial clock input. 25 CS I Chip Select (active LOW) Pin must be LOW to access WTS701 device. 26 R/ B O Ready/busy signal; This pin defaults HIGH indicating the device is ready for data transfer. The pin is driven LOW to handshake a pause in SPI data transfer and Open Drain. |
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