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AT49F040A-55TI Datasheet(PDF) 2 Page - ATMEL Corporation |
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AT49F040A-55TI Datasheet(HTML) 2 Page - ATMEL Corporation |
2 / 16 page 2 AT49F040A 3359B–FLASH–10/04 When the device is deselected, the CMOS standby current is less than 70 µA. To allow for simple in-system reprogrammability, the AT49F040A does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F040A is per- formed by erasing a block of data and then programming on a byte-by-byte basis. The byte programming time is a fast 20 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally con- trols the erase operations. There are two 8K byte parameter block sections, eight main memory blocks, and one boot block. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out fea- ture to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram CONTROL LOGIC Y DECODER PARAMETER BLOCK 1 (8K BYTES) BOOT BLOCK (16K BYTES) OE WE CE RESET ADDRESS INPUTS VCC GND AT49F040A DATA INPUTS/OUTPUTS I/O7 - I/O0 8 X DECODER PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (32K BYTES) MAIN MEMORY BLOCK 2 (64K BYTES) MAIN MEMORY BLOCK 3 (64K BYTES) MAIN MEMORY BLOCK 4 (64K BYTES) MAIN MEMORY BLOCK 8 (64K BYTES) MAIN MEMORY BLOCK 7 (64K BYTES) MAIN MEMORY BLOCK 6 (64K BYTES) MAIN MEMORY BLOCK 5 (64K BYTES) PROGRAM DATA LATCHES Y-GATING INPUT/OUTPUT BUFFERS 1FFFF 10000 0FFFF 08000 3FFFF 30000 2FFFF 20000 07FFF 06000 05FFF 04000 03FFF 00000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 |
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