CY7C43642
CY7C43662
CY7C43682
Document #: 38-06019 Rev. *B
Page 7 of 30
Empty/Output Ready Flags (EFA/ORA, EFB/ORB)
These are dual-purpose flags. In the FWFT Mode, the Output
Ready
(ORA,
ORB)
function
is
selected.
When
the
Output-Ready flag is HIGH, new data is present in the FIFO
output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and
attempted FIFO reads are ignored. (See footnote #1)
In the CY Standard Mode, the Empty Flag (EFA, EFB) function
is selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads
are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is incremented
each time a new word is clocked to its output register. The
state machine that controls an Output Ready flag monitors a
write pointer and read pointer comparator that indicates when
the FIFO SRAM status is empty, or empty+1.
In FWFT Mode, from the time a word is written to a FIFO, it
can be shifted to the FIFO output register in a minimum of
three cycles of the Output Ready flag synchronizing clock.
Therefore, an Output Ready flag is LOW if a word in memory
is the next data to be sent to the FIFO output register and three
cycles have not elapsed since the time the word was written.
The Output Ready flag of the FIFO remains LOW until the third
LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and
shifting the word to the FIFO output register.
In the CY Standard Mode, from the time a word is written to a
FIFO, the Empty flag will indicate the presence of data
available for reading in a minimum of two cycles of the Empty
flag synchronizing clock. Therefore, an Empty Flag is LOW if
a word in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Empty flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
clock occurs, forcing the Empty flag HIGH; only then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the first synchronization cycle.
Full/Input Ready Flags (FFA/IRA, FFB/IRB)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IRA and IRB) function is selected. In CY Standard Mode, the
Full Flag (FFA and FFB) function is selected. For both timing
modes, when the Full/Input Ready flag is HIGH, a memory
location is free in the SRAM to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and
attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FIFO is synchronized to the port
clock that writes data to its array. For both FWFT and CY
Standard modes, each time a word is written to a FIFO, its
write pointer is incremented. The state machine that controls
a Full/Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM status
is full, or full–1. From the time a word is read from a FIFO, its
previous memory location is ready to be written to in a
minimum of two cycles of the Full/Input Ready flag synchro-
nizing clock. Therefore, an Full/Input Ready flag is LOW if less
than two cycles of the Full/Input Ready flag synchronizing
clock have elapsed since the next memory write location has
been read. The second LOW-to-HIGH transition on the
Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at time tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle.
Almost Empty Flags (AEA, AEB)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, or almost empty+1. The Almost Empty
state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset
values during a FIFO reset, programmed from Port A, or
programmed serially (see Almost Empty flag and Almost Full
flag offset programming above). An Almost Empty flag is LOW
when its FIFO contains X or less words and is HIGH when its
FIFO contains (X+1) or more words.[2]
Two LOW-to-HIGH transitions of the Almost Empty flag
synchronizing clock are required after a FIFO write for its
Almost Empty flag to reflect the new level of fill. Therefore, the
Almost Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An Almost Empty flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an Almost Empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle.
Almost Full Flags (AFA, AFB)
The Almost Full flag of a FIFO is synchronized to the port clock
that writes data to its array. The state machine that controls an
Almost Full flag monitors a write pointer and read pointer
comparator that indicates when the FIFO SRAM status is
almost full, or almost full–1. The Almost Full state is defined by
the contents of register Y1 for AFA and register Y2 for AFB.
These registers are loaded with preset values during a FIFO
reset, programmed from Port A, or programmed serially (see
Almost Empty flag and Almost Full flag offset programming
above). An Almost Full flag is LOW when the number of words
in its FIFO is greater than or equal to (1024–Y), (4096–Y), or
(16384–Y) for the CY7C436X2 respectively. An Almost Full
flag is HIGH when the number of words in its FIFO is less than
or equal to [1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for
the CY7C436X2 respectively. (See footnote #2)
Two LOW-to-HIGH transitions of the Almost Full flag synchro-
nizing clock are required after a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
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