CY7C43642AV
CY7C43662AV
CY7C43682AV
Document #: 38-06020 Rev. *C
Page 8 of 30
programmed serially (see Almost Empty flag and Almost Full
flag offset programming, above). An Almost Full flag is LOW
when the number of words in its FIFO is greater than or equal
to (1024 – Y), (4096 – Y), or (16384 – Y) for the
CY7C436X2AV, respectively. An Almost Full flag is HIGH
when the number of words in its FIFO is less than or equal to
[1024 – (Y + 2)], [4096 – (Y + 2)], or [16384 – (Y + 2)], for the
CY7C436X2AV respectively.[1]
The Almost Full flag is set HIGH by the first LOW-to-HIGH
transition of its synchronizing clock after two FIFO Reads that
reduce
the
number
of
words
in
memory
to
[1024/4096/16384 – (Y + 2)]. A LOW-to-HIGH transition of an
Almost Full flag synchronizing clock begins the first synchro-
nization cycle if it occurs at time tSKEW2 or greater after the
Read that reduces the number of words in memory to
[1024/4096/16384 – (Y + 2)]. Otherwise, the subsequent
synchronizing clock cycle will be the first synchronization
cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass register to pass command and
control information between Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation.
A LOW-to-HIGH transition on CLKA writes A0-35 data to the
Mail1 Register when a Port A Write is selected by CSA, W/RA,
and ENA with MBA HIGH.
A LOW-to-HIGH transition on CLKB writes B0-35 data to the
Mail2 Register when a Port B Write is selected by CSB, W/RB,
and ENB with MBB HIGH.
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted Writes to a mail register are
ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the port
Mailbox Select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Port B Read is
selected by CSB, W/RB, and ENB with MBB HIGH.
The Mail2 register Flag (MBF2) is set HIGH by a
LOW-to-HIGH transition on CLKA when a Port A Read is
selected by CSA, W/RA, and ENA with MBA HIGH.
The data in a mail register remains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on mailbox data.
Retransmit (RT1, RT2)
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary. The retransmit
function applies to CY Standard mode only.
The number of 36-/18-/9-bit words written into the FIFO should
be less than full depth minus 2/4/8 words between the reset of
the FIFO (master or partial) and Retransmit setup. A LOW
pulse on RT1, RT2 resets the internal Read pointer to the first
physical location of the FIFO. CLKA and CLKB may be
free-running but ENB must be deasserted during and tRTR af-
ter the retransmit pulse. With every valid Read cycle after re-
transmit, previously accessed data is read and the Read point-
er is incremented until it is equal to the Write pointer. Flags are
governed by the relative locations of the Read and Write point-
ers and are updated during a retransmit cycle. Data written to
the FIFO after activation of RT1, RT2 are transmitted also.
Table 1. Flag Programming
FS1
FS0
MRST1
MRST2
X1 and Y1 Registers[2]
X2 and Y2 Registers[3]
H
H
↑
X
64
X
H
H
X
↑
X
64
H
L
↑
X
16
X
H
L
X
↑
X
16
L
H
↑
X
8
X
L
H
X
↑
X
8
L
L
↑
↑
Programming via Port A
Programming via Port A
Table 2. Port A Enable Function
CSA
W/RA
ENA
MBA
CLKA
A0–35
Port Function
H
X
X
X
X
In high-impedance state
None
L
H
L
X
X
In high-impedance state
None
L
H
H
L
↑
In high-impedance state
FIFO1 Write
L
H
H
H
↑
In high-impedance state
Mail1 Write
L
L
L
L
X
Active, FIFO2 output register
None
Notes:
2.
X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
3.
X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
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