LMF90CIJ datasheet(10/22 Pages) NSC

Part #	LMF90CIJ

Description	4th-Order Elliptic Notch Filter

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Manufacturer	NSC [National Semiconductor (TI)]

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Pin Descriptions

W (Pin 1)

This three-level logic input sets the width of

the notch Notch width is fc2–fc1 (see Figure

1 ) When W is tied to V

a

(pin 14) GND (pin

13) or V

b

(pin 8) the notch width is 055 f0

026 f0 or 0127 f0 respectively

R (Pin 2)

This three-level logic input sets the ratio of

the clock frequency (fCLK) to the center fre-

quency (f0) When R is tied to V

a

GND or

V

b

the clock-to-center-frequency ratio is

33331 501 or 1001 respectively

LD (Pin 3)

This three-level logic input sets the division

factor of the clock frequency divider When

LD is tied to V

a

GND or V

b

the division

factor is 716 596 or 2 respectively

XTAL2 (Pin 4) This is the output of the internal crystal os-

cillator When using the internal oscillator

the crystal should be tied between XTAL2

and XTAL1 (The capacitors are internal

no external capacitors are needed for the

oscillator to operate) When not using the

internal oscillator this pin should be left

open

XTAL1 (Pin 5) This is the crystal oscillator input When us-

ing the internal oscillator the crystal should

be tied between XTAL1 and XTAL2 XTAL1

can also be used as an input for an external

clock signal swinging from V

a

to V

b

The

frequency of the crystal or the external

clock will be divided internally by the clock

divider as determined by the programming

voltage on pin 3

CLK (Pin 6)

This is the filter clock pin The clock signal

appearing on this pin is the filter clock

(fCLK) When using the internal crystal oscil-

lator or an external clock signal applied to

pin 5 while pin 7 is tied to V

a

the CLK pin is

the output of the divider and can be used to

drive other LMF90s with its rail-to-rail output

swing When not using the internal crystal

oscillator or an external clock on pin 5 the

CLK pin can be used as a CMOS or TTL

clock input provided that pin 7 is tied to

GND or V

b

For best performance the duty

cycle of a clock signal applied to this pin

should be near 50% especially at higher

clock frequencies

XLS (Pin 7)

This is a three-level logic pin When XLS is

tied to V

a

the crystal oscillator and fre-

quency divider are enabled and CLK (pin 6)

is an output When XLS is tied to GND (pin

13) the crystal oscillator and frequency di-

vider are disabled and pin 6 is an input for a

clock swinging between V

b

and V

a

When

XLS is tied to V

b

the crystal oscillator and

frequency divider are disabled and pin 6 is a

TTL level clock input for a clock signal

swinging between GND and V

a

or between

V

b

and GND

V

b

(Pin 8)

This is the negative power supply pin It

should be bypassed with at least a 01 mF

capacitor

For

single-supply

operation

connect this pin to system ground

VOUT (Pin 9)

This is the filter output

D (Pin 10)

This two-level logic input is used to set the

depth of the notch (the attenuation at f0)

When D is tied to GND or V

b

the typical

notch depth is 48 dB or 39 dB respective-

ly Note however that the notch depth is

also dependent on the width setting (pin

1) See the Electrical Characteristics for

tested limits

VIN2 (Pin 11)

This is the input to the difference amplifier

section of the notch filter

VIN1 (Pin 12)

This is the input to the internal bandpass

filter This pin is normally connected to pin

11 For wide bandwidth applications an

anti-aliasing filter can be inserted between

pin 11 and pin 12

GND (Pin 13)

This is the analog ground reference for the

LMF90 In split supply applications GND

should

be

connected

to

the

system

ground When operating the LMF90 from a

single positive power supply voltage pin

13 should be connected to a ‘‘clean’’ refer-

ence voltage midway between V

a

and

V

b

V

a

(Pin 14)

This is the positive power supply pin It

should be bypassed with at least a 01 mF

capacitor

10 Definition of Terms

Amax the maximum amount of gain variation within the fil-

ter’s passband (See

Figure 1 ) For the LMF90 AMax is

nominally equal to 025 dB

Amin the minimum attenuation within the notch’s stopband

(See

Figure 1 ) This parameter is adjusted by programming

voltage applied to pin 10 (D)

Bandwidth (BW) or Passband Width

the difference in fre-

quency between the notch filter’s two cutoff frequencies

Cutoff Frequency

for a notch filter one of the two fre-

quencies fC1 and fC2 that define the edges of the pass-

band At these two frequencies the filter has a gain equal to

the passband gain

fCLK the frequency of the clock signal that appears at the

CLK pin This frequency determines the filter’s center fre-

quency Depending on the programming voltage on pin 2

(R) fCLK will be either 3333 50 or 100 times the center

frequency of the notch

f0 or fNotch the center frequency of the notch filter This

frequency is measured by finding the two frequencies for

which the gain b3 dB relative to the passband gain and

calculating their geometrical mean

Passband

for a notch filter frequencies above the upper

cutoff frequency (fC2 in Figure 1 ) and below the lower cutoff

frequency (fC1 in Figure 1 )

10

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