AD7322

Preliminary Technical Data

TIMING SPECIFICATIONS

Parameter

Unit

Description

10

kHz min

20

MHz max

ns max

50

ns max

Minimum Time between End of Serial Read and Next Falling Edge of CS

10

ns min

Minimum CS Pulse width

10

ns min

CS to SCLK Setup Time

20

ns max

TBD

ns max

Data Access Time after SCLK Falling Edge.

ns min

SCLK Low Pulsewidth

ns min

SCLK High Pulsewidth

10

ns min

SCLK to Data Valid Hold Time

25

ns max

10

ns min

TBD

ns min

DIN set-up time prior to SCLK falling edge

5

ns min

DIN hold time after SCLK falling edge

1

µs max

Power up from Auto Standby

TBD

µs max

Power up from Full Shutdown/Auto Shutdown Mode

Figure 2. Serial Interface timing Diagram

Rev. PrE | Page 5 of 18