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AND8090D Datasheet(PDF) 9 Page - ON Semiconductor |
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AND8090D Datasheet(HTML) 9 Page - ON Semiconductor |
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9 / 20 page  AND8090/D http://onsemi.com 9 Differential Inputs (Single−Ended Mode) – Either input of a differential pair may be used individually if the unused input of the differential pair is connected to VBB (the switching reference voltage). The switching reference voltage is provided by many differential devices. Figure 19 illustrates the use of the true input as the single−ended input. Note that the unused inverted output is terminated in the same fashion as the true output. Figure 19. Differential Input in Single−Ended Mode VIH VIL 50% 50% VOH VOL D1 D1 VBB Q1 Q1 Use Q1 Termination The switching reference voltage provides a switching point that is approximately halfway between the HIGH and LOW levels. As an example, the MC100EP116 data sheet specifies the following switching reference voltage range for the 5.0 V PECL mode. The MC100EP116 50% point range previously calculated is listed below the VBB range. 3475 mV v VBB v 3675 mV 3483 mV v 50% Point v 3748 mV Note that the VBB range is very close to the 50% point range. This is true because the switching reference voltage provides a switching point for a differential input in single−ended mode that is analogous to the 50% point range for normal single−ended inputs. TIMING CHARACTERISTICS Output Rise and Fall Times ECL Output Devices – The output rise time for ECL devices is the time required to rise from the 20% level to the 80% level of the output rising edge. The output fall time for ECL devices is the time required to fall from the 80% level to the 20% level of the output falling edge. The output rise and fall times for devices with ECL outputs is shown in Figure 20. Figure 20. ECL Output Rise and Fall Times tR tF HIGH LOW 20% 80% Non−ECL Output Devices – Refer to the translator data sheets as different conditions are used to specify the output rise and fall times. One type of condition specifies output rise and fall times between the 10% and 90% output levels. For example, the rise and fall times for the MC100ELT21 PECL to TTL translator are specified between the 10% and 90% output levels as shown in Figure 21. Figure 21. TTL Output Rise and Fall Time Percentages tR tF 90% 10% HIGH LOW Another type of test condition specifies non−ECL output rise and fall times between fixed output voltage levels. For example, the rise and fall times for the MC100EPT21 LVPECL to LVTTL translator are specified between fixed output voltages of 0.8 V and 2.0 V as shown in Figure 22. Figure 22. LVTTL Output Rise and Fall Time Levels tR tF HIGH LOW VO = 2.0 V VO = 0.8 V |
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