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DEVICE CHARACTERISTICS

CDC5806

SCAS760A – MARCH 2004 – REVISED JULY 2004

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OVERALL

Supply current

Test load

35

45

mA

1.1

mA

Supply voltage threshold for power up control circuit

2

V

LVCMOS

LVCMOS input voltage

–1.2

V

REF_IN input current

±5

µA

SELECT input current

±55

µA

High-level output voltage

V

Low-level output voltage

0.4

V

–5

High-level output current

–35

mA

–75

5

Low-level output current

35

mA

75

AC

Input capacitance (Ref_IN)

2

pF

Output accuracy VIDCLK, CPUCLK, ASICCLK,

±1 ppm

USBCLK, MCCLK (38.4 MHz, 19.2 MHz, 12 MHz)

Output accuracy AUDCLK (16.9344 MHz, 12.288 MHz)

±40 ppm

PLL start up lock time

See Figure 2

0.5

ms

PLL lock time after frequency change on AUDCLK

See Figure 2

0.5

ms

odc

Duty cycle for MCCLK

Threshold = VDD/2

47%

50%

53%

Duty cycle for VIDCLK, AUDCLK, CPUCLK, ASICCLK,

odc

Threshold = VDD/2

45%

50%

55%

USBCLK

Rise and fall time of the output

2

ns

VIDCLK

75

150

(74.175824 MHz)

CPUCLK (64 MHz)

60

150

USBCLK (48 MHz)

65

150

MCCLK (38.4 MHz)

65

150

Peak-to-peak period jitter for

10,000 cycles

ps

ASICCLK (32 MHz)

60

150

MCCLK (19.2 MHz)

70

150

AUDCLK (16.9344 MHz)

75

150

AUDCLK (12.288 MHz)

85

150

MCCLK (12 MHz)

65

150

(1)

This parameter is assured by design as a result of the chosen settings of the internal dividers in the PLL's.

5