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CS5540 Datasheet(PDF) 8 Page - Cirrus Logic |
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CS5540 Datasheet(HTML) 8 Page - Cirrus Logic |
8 / 22 page CS5540 8 DS503PP1 SWITCHING CHARACTERISTICS (T A = 25 °C; VA+ = +3.0 V ±5% VA- = 0 V, VD+ = 3.0 V ±5%, DGND = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF) Notes: 18. Device parameters are specified with 32.768 kHz clock; however, clocks up to 40 kHz can be used for increased throughput. 19. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 20. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Units Master Clock Frequency: External Clock Internal Oscillator (Note 18) MCLK 5 - - 32.768 40 - kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 19) Any Digital Input Except SCLK SCLK SDO Output trise - - - - - 50 1.0 100 - µs µs ns Fall Times (Note 19) Any Digital Input Except SCLK SCLK SDO Output trise - - - - - 50 1.0 100 - µs µs ns Start-up Oscillator Start-up Time XTAL = 32.768 kHz (Note 20) tost -500 - ms Power-on Reset Period tpor -490 - MCLK cycles Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz Serial Clock Pulse Width High Pulse Width Low t1 t2 250 250 - - - - ns ns CS Enabled to SCLK Rising t3 50 - - ns SCLK falling prior to Chip Select Disabled t4 100 - - ns SDO Read Timing CS to Data Valid t5 -- 150 ns SCLK Falling to New Data Bit t6 -- 150 ns CS Rising to SDO Hi-Z t7 -- 150 ns |
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