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EA218EI0B Datasheet(PDF) 10 Page - Zarlink Semiconductor Inc |
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EA218EI0B Datasheet(HTML) 10 Page - Zarlink Semiconductor Inc |
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10 / 28 page  PRELIMINARY INFORMATION XpressFlow-2020 Series – EA218E Ethernet Switch Chipset 8-Port 10Mb Ethernet Access Controller © 1998 Zarlink Semiconductor, Inc. 9 Rev.2.1 – February, 1999 2.1.2 Supported Memory Configurations Read/Write Chip Select and High Address Bits Chip #3 Chip #2 Chip #1 Chip #0 RAM Chip Size # of RAM Chips Total Buffer Memory Size L_WE[3]# L_A[19] / L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 32k x 32 1 128k bytes ---- ---- ---- ---- ---- ---- L_WE[0]# L_OE[0]# 2 256k bytes ---- ---- ---- ---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 4 512k bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 64k x 32 1 256k bytes ---- ---- ---- ---- ---- ---- L_WE[0]# L_OE[0]# 2 512k bytes ---- ---- ---- ---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 4 1M bytes L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 128k x32 1 512k bytes ---- ---- ---- ---- ---- ---- L_WE[0]# L_OE[0]# 2 1M bytes ---- ---- ---- ---- L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# 256k x32 1 1M bytes ---- L_A[19] ---- ---- ---- ---- L_WE[0]# L_OE[0]# 2.1.3 Bus Cycle Waveforms A1 A2 A3 A3+1 A3+2 A3+3 A4 A4+1 A4+2 A4+3 A5 A6 D2 D3+1 D3+2 D3+3 D4 D4+1 D4+2 D4+3 D5 D6 D1 D3 L_CLK L_ADSC# L_CS# L_A[19:2] L_WE[3:0]# L_BWE[3:0]# L_OE[3:0]# L_D[31:0] (Wr) L_D[31:0] (Rd) Typical Local Memory Access Operations |
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