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IDT82V2084 Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT82V2084 Datasheet(HTML) 7 Page - Integrated Device Technology |
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7 / 75 page  7 INDUSTRIAL TEMPERATURE RANGES QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LIST OF FIGURES Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82V2084 TQFP128 Package Pin Assignment .......................................................... 8 Figure-3 E1 Waveform Template Diagram .................................................................................. 14 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 14 Figure-5 DSX-1 Waveform Template .......................................................................................... 14 Figure-6 T1 Pulse Template Test Circuit ..................................................................................... 15 Figure-7 Receive Path Function Block Diagram .......................................................................... 20 Figure-8 Transmit/Receive Line Circuit ....................................................................................... 20 Figure-9 Monitoring Receive Line in Another Chip ...................................................................... 21 Figure-10 Monitor Transmit Line in Another Chip .......................................................................... 21 Figure-11 G.772 Monitoring Diagram ............................................................................................ 22 Figure-12 Jitter Attenuator ............................................................................................................. 23 Figure-13 LOS Declare and Clear .................................................................................................24 Figure-14 Analog Loopback .......................................................................................................... 27 Figure-15 Digital Loopback ............................................................................................................ 27 Figure-16 Remote Loopback ......................................................................................................... 27 Figure-17 Auto Report Mode ......................................................................................................... 29 Figure-18 Manual Report Mode ..................................................................................................... 30 Figure-19 TCLK Operation Flowchart ............................................................................................ 31 Figure-20 Serial Processor Interface Function Timing .................................................................. 32 Figure-21 JTAG Architecture ......................................................................................................... 54 Figure-22 JTAG State Diagram ..................................................................................................... 57 Figure-23 Transmit System Interface Timing ................................................................................ 65 Figure-24 Receive System Interface Timing ................................................................................. 65 Figure-25 E1 Jitter Tolerance Performance .................................................................................. 66 Figure-26 T1/J1 Jitter Tolerance Performance .............................................................................. 66 Figure-27 E1 Jitter Transfer Performance ..................................................................................... 68 Figure-28 T1/J1 Jitter Transfer Performance ................................................................................ 68 Figure-29 JTAG Interface Timing .................................................................................................. 69 Figure-30 Serial Interface Write Timing .........................................................................................70 Figure-31 Serial Interface Read Timing with SCLKE=1 ................................................................ 70 Figure-32 Serial Interface Read Timing with SCLKE=0 ................................................................ 70 Figure-33 Non_multiplexed Motorola Read Timing ....................................................................... 71 Figure-34 Non_multiplexed Motorola Write Timing ....................................................................... 72 Figure-35 Non_multiplexed Intel Read Timing .............................................................................. 73 Figure-36 Non_multiplexed Intel Write Timing .............................................................................. 74 |
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