CMOS SDRAM

- 11

SDRAM 64Mb H-die (x32)

Rev. 1.3 February. 2004

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Note :

Parameter

Symbol

50

55

60

70

Unit

Note

Min

Max

Min

Max

Min

Max

Min

Max

CLK cycle time

CAS Latency=3

5

1000

5.5

1000

6

1000

7

1000

ns

1

CAS Latency=2

10101010

CLK to valid

output delay

CAS Latency=3

-4.5

-5.0

-5.5

-5.5

ns

1, 2

CAS Latency=2

-

6-6-6-6

Output data hold time

2-2-2-2

-

ns

2

CLK high pulse

width

CAS Latency=3

2-2-

2.5

-

3

-

ns

3

CAS Latency=2

3

-3-3-

3

-

CLK low

pulse width

CAS Latency=3

2-2-

2.5

-

3

-

ns

3

CAS Latency=2

3

-3-3-

3

-

Input setup time

CAS Latency=3

1.5

-

1.5

-

1.5

-

1.75

-

ns

3

CAS Latency=2

2.5

-2.5

-2.5

-2.5

-

Input hold time

1-1-1-1

-

ns

3

CLK to output in Low-Z

1-1-1-1

-

ns

2

CLK to output

in Hi-Z

CAS latency=3

-4.5

-5.0

-5.5

-5.5

ns

-

CAS latency=2

-

6-6-6-6