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AFBR-5972EZ Datasheet(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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AFBR-5972EZ Datasheet(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED |
2 / 7 page 2 The opto-electrical subassemblies utilize a high volume assembly process together with low cost lens elements which result in a cost effective building block. It consists of the active III-V devices, IC chips and various surface mounted pas- sive components. There are eight signal pins, four EMI shield solder posts and two mounting posts, which exit the bottom of the housing. The solder posts are isolated from the internal circuit of the transceiver and are to be connected to chassis ground. The mounting posts are to provide mechanical strength to hold the transceiver to the application board. Pin Description Pin 1 TData+: Transmitter data in positive. This input is an LVDS compatible differential line. Pin 2 TData-: Transmitter data in negative. This input is an LVDS compatible differential line. Pin 3 TxVCC: Transmitter power supply pin. Provide +3.3 V DC via a transmitter power supply filter circuit. Locate the power supply filter circuit as close as possible to the TxVcc pin. Pin 4 GND: Common ground pin. Directly connect this pin to the signal ground plane of the host board. Pin 5 RxVCC: Receiver power supply pin. Provide +3.3 V DC via a receiver power supply filter circuit. Locate the power supply filter circuit as close as possible to the RxVcc pin. Pin 6 RSSI: Receiver signal strength pin, delivers a DC output current proportional to the average incoming light power. Pin 7 RData+: Receiver data out positive. This data line is an LVDS compatible differential output line which should be properly terminated. In absence of an optical input signal, this line is squelched. Pin 8 RData-: Receiver data out negative. This data line is an LVDS compatible differential output line which should be properly terminated. In absence of an optical input signal, this line (same as RData+) is squelched. Shield Shield This is to be connected to the equipment chassis ground. Figure 2. PCB footprint and pinout diagram Top V iew NOT E S : 1) Dimens ion: mm 2) G eneral tolerance: ± 0.05 3) R ecommended P C B T hicknes s 1.57± 0.05 4) P in des cription 0 3.05 6.35 8.89 0 3.73 3.18 8.66 3.2 0.1 + (2x) MOUNT P OS T UNP LAT E D (2x) ST ANDOF F AR E A (4 x 1.9 x 1) 1 2 3 4 5 6 7 8 ST ANDOF F AR E A (2 x 0.65 x 1.03) Front PIN F UNC 1T D+ 2T D- 3T xV cc 4G ND 5 RxV cc 6 RSSI 7R D+ 8 RD- 0.9 0.1 + (8x) 1.6 0.1 + S HIE LD G ND (2x) |
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