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MAX3272 Datasheet(PDF) 7 Page - Maxim Integrated Products |
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MAX3272 Datasheet(HTML) 7 Page - Maxim Integrated Products |
7 / 14 page Two control voltages VASSERT, and VDEASSERT, define the LOS assert and deassert levels. To prevent LOS chatter in the region of the programmed threshold, approximately 3.3dB of hysteresis is built into the LOS assert/deassert function. Once asserted, LOS is not deasserted until the input amplitude rises to the required level (VDEASSERT). To facilitate interfacing with +5V modules, the LOS and LOS pins on the MAX3272 do not have internal ESD protection. If ESD protection is desired, a low-capaci- tance Schottky diode or diode array structure, such as the MAX3202E, is recommended (see the Typical Operating Circuits). The LOS and LOS pins on the MAX3272A include ESD protection and, as a result, cannot be interfaced with +5V modules. Gain Stage The high-bandwidth gain stage provides approximately 42dB of gain. Offset-Correction Loop Due to the high gain of the amplifier, the MAX3272/ MAX3272A are susceptible to DC offsets in the signal path. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is removed by the offset- cancellation loop. An external capacitor is required between CAZ1 and CAZ2 to decouple the offset-can- cellation loop and determine the lower 3dB frequency of the signal path. +3.3V, 2.5Gbps Low-Power Limiting Amplifiers _______________________________________________________________________________________ 7 Interface Schematics IN+ IN- 110 Ω GND ESD STRUCTURES VCC 540 Ω 540 Ω 0.25pF 0.25pF Figure 3. Input Circuit GND ESD STRUCTURE VCC LOS 8k Ω Figure 4a. LOS Output Circuit for MAX3272 GND ESD STRUCTURE VCC LOS 8k Ω Figure 4b. LOS Output Circuit for MAX3272A |
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Similar Description - MAX3272 |
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