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MAX5735 Datasheet(PDF) 10 Page - Maxim Integrated Products

Part # MAX5735
Description  32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX5735 Datasheet(HTML) 10 Page - Maxim Integrated Products

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32-Channel, 16-Bit, Voltage-Output
DACs with Serial Interface
10
______________________________________________________________________________________
TIMING CHARACTERISTICS—DVDD = +2.7V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCLK
0
25
MHz
SCLK Pulse-Width High
tCH
10
ns
SCLK Pulse-Width Low
tCL
10
ns
SCLK Fall to
CS Fall Setup Time
tSCS
10
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
18
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF
25
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF
25
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
CLR Pulse-Width Low
tCLR
20
ns
TIMING CHARACTERISTICS—DVDD = +4.75V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCLK
033
MHz
SCLK Pulse-Width High
tCH
10
ns
SCLK Pulse-Width Low
tCL
10
ns
SCLK Fall to
CS Fall Setup Time
tSCS
6ns
CS Fall to SCLK Fall Setup Time
tCSS
5ns
CS Rise to SCLK Fall
tCS1
At end of cycle in SPI mode only
15
ns
SCLK Fall to
CS Rise Setup Time
tCS2
0ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
2ns
SCLK Fall to DOUT Fall
tSCL
Load capacitance = 20pF
20
ns
SCLK Fall to DOUT Rise
tSDH
Load capacitance = 20pF
20
ns
CS Pulse-Width High
tCSPWH
50
ns
CS Pulse-Width Low
tCSPWL
20
ns
LDAC Pulse-Width Low
tLDAC
20
ns
CLR Pulse-Width Low
tCLR
20
ns


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