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ADNS-5070 Datasheet(PDF) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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ADNS-5070 Datasheet(HTML) 11 Page - AVAGO TECHNOLOGIES LIMITED |
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11 / 41 page  11 Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Notes Operating Temperature TA 0 40 °C Power supply voltage VDD 4.10 5.0 5.5 Volts Register values retained for voltage transients below 4.10V but greater than 3.9V. Power supply rise time VRT 100 ms Supply noise VN 100 mV Peak to peak within 0-50 MHz bandwidth Serial Port Clock Frequency fSCLK 3 MHz 550% duty cycle. Resonator Impedance XRES 55 Ω Distance from lens reference plane to surface Z 2.3 2.4 2.5 mm Results in ±0.1 mm DOF, (See Figure 8) Speed S 30 in/sec Acceleration A 8 g Light level onto IC IRRINC 80 100 25,000 30,000 mW/m2 λ = 639 nm λ = 875 nm SDIO read hold time tHOLD 100 ns Hold time for valid data (Refer to Figure 20) SDIO serial write-write time tSWW 100 us Time between two write commands. (Refer to Figure 22) SDIO serial write-read time tSWR 100 us Time between write and read operation. (Refer to Figure 23) SDIO serial read-write time tSRW 250 ns Time between read and write operation. (Refer to Figure 24) SDIO serial read-read time tSRR 250 ns Time between two read commands. (Refer to Figure 24) SPI Read Address-Data Delay tSRAD 4 us From rising SCLK for last bit of the address byte, to falling SCLK for first bit of data being read. (Refer to Figure 24) Data delay after PD deactivated tCOMPUTE 3.1 ms After tCOMPUTE, all registers contain data from first image after wakeup from Power-Down mode. Note that an additional 75 frames for AGC stabilization may be required if mouse movement occurred while Power Down. (refer to Figure 9) SDIO write setup time tsetup 60 ns Data valid time before the rising of SCLK. (refer to Figure 17) |
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Similar Description - ADNS-5070 |
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