2.2 PROGRAMMABLE REFERENCE DIVIDERS (Main and Aux R Counters)

2.2.1 Aux_R Register

If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 22-bit shift register into the Aux_R register when Load Enable

(LE) signal goes high. The Aux_R register sets the Aux PLL’s 15-bit R-counter divide ratio and various programmable modes. The

divide ratio is put into the Aux_R_CNTR[14:0] field. The divider ratio must be

≥ 2. For the description of bits Aux_R15–Aux_R19

see Section 2.4.

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

21

20

19

18

17

16

15

14

13

12

11

10

98765432

1

0

Data Field

Address Field

Aux_R

Aux_R_CNTR[14:0]

00

2.2.2 Main_R Register

If the ADDRESS[1:0] field is set to 1 0, data is transferred from the 22-bit shift register into the Main_R register which sets the

Main PLL’s 15-bit R-counter divide ratio when Load Enable (LE) signal goes high. The divide ratio is put into the

Main_R_CNTR[14:0] field. The divider ratio must be

≥ 2. For the description of bits Main_R15–Main_R19 see Section 2.4.

Most Significant Bit

SHIFT REGISTER BIT LOCATION

Least Significant Bit

21

20

19

18

17

16

15

14

13

12

11

10

98765432

1

0

Data Field

Address Field

Main_R

Main_R_CNTR[14:0]

10

2.2.3 Reference Divide Ratio (Main and Auxiliary R-Counters)

If the ADDRESS[1:0] field is set to00or10(00 for Aux and 10 for Main) data is transferred MSB first from the 22-bit shift register

into a latch which sets the respective 15-bit R-counter. Serial data format is shown below.

Main_R_CNTR[14:0] or Aux_R_CNTR[14:0]

Divide Ratio

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

2

000000000000010

3

000000000000011

•

•••••••••••••••

32,767

111111111111111

Note: R-counter divide ratio must be from 2 to 32,767.

2.3 PROGRAMMABLE FEEDBACK [N] DIVIDERS

2.3.1 Aux_N Register

If the ADDRESS[1:0] field is set to 0 1, data is transferred from the 22-bit shift register into the Aux_N register which sets the Aux-

iliary PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow

counter, Aux_A_CNTR[4:0], and a 13-bit programmable counter, Aux_B_CNTR[12:0]. Serial data format is shown below.

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