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TMS320C6412GNZ500 Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320C6412GNZ500 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 159 page  Revision History 3 April 2003 − Revised June 2004 SPRS219D Revision History This data sheet revision history highlights the technical changes made to the SPRS219C device-specific data sheet to make it an SPRS219D revision. Scope: Applicable updates to the C64x device family, specifically relating to the TMS320C6412 device, have been incorporated. Added the device-specific information supporting the TMS320C6412 silicon revision 1.0 device which is now in the production data (PD) stage of development. Added the C6412 extended temperature devices (A-500) device-specific information (for both GDK and GNZ packages and operating at 1.4-V internal). Highlights: D Updated/changed the C6412 device status from “Advance Information” (AI) to “Production Data” (PD) D Updated/changed timings for Electrical Characteristics, Input and Output Clocks Timing; Asynchronous Memory; Reset Timing; Multichannel Buffered Serial Port; and JTAG Timing. D Corrected timing parameter signal descriptions to match terminal functions D Updated/added Power-Down Modes Logic section and references PAGE(s) NO. ADDS/CHANGES/DELETES Global change: Changed all EMIF signal names to be specific to EMIFA Updated the EMAC/MDIO peripherals detailed descriptions, the EMAC Control Registers table, the EMAC Statistics Registers table, and the MDIO Registers table to support an EMAC module that has 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel and does not support receive quality of service (QOS). Updated/changed the C6412 device status from “Advance Information” (AI) to “Production Data” (PD) 19 Features section: “10/100 Mb/s Ethernet MAC (EMAC)” feature: Changed “8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels” to “8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel” 21 Description section: “With performance of up to 4800 million instructions per second (MIPS) ...” paragraph: Changed “The C6412 can produce four 32-bit multiply-accumulates (MACs) per cycle ...” to “The C6412 can produce four 16-bit multiply-accumulates (MACs) per cycle ...” 22 Characteristics of the C6412 Processor table: Updated table to include A-500 extended temperature device Updated/changed table to include “TMS” and “Extended Temperature” device part numbers 29 L2 Architecture Expanded section: Added new section Added Figure 1−5, TMS320C6412 L2 Architecture Memory Configuration 30 EMIFA Registers table: Split the “Reserved” row between hex address range “0180 0024 − 0180 0040” Added the Peripheral device transfer (PDT) control register (PDTCTL) to the hex address location 0180 0040 30 L2 Cache Registers (C64x) table: Split the “Reserved” row between hex address range “0184 0004 − 0184 1FFC” Added the L2 EDMA access control register (EDMAWEIGHT) to the hex address location 0184 1000 |
Similar Part No. - TMS320C6412GNZ500 |
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Similar Description - TMS320C6412GNZ500 |
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